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2010 – 2019
- 2019
[j8]Nobutaka Kito, Ryota Odaka, Kazuyoshi Takagi:
Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing. IEICE Trans. Electron. 102-C(7): 607-611 (2019)- [j7]Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi
:
Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses. IPSJ Trans. Syst. LSI Des. Methodol. 12: 78-80 (2019) - [j6]Nobutaka Kito, Naofumi Takagi:
Concurrent Error Detectable Carry Select Adder with Easy Testability. IEEE Trans. Computers 68(7): 1105-1110 (2019) - 2017
- [j5]Nobutaka Kito, Kazushi Akimoto, Naofumi Takagi:
Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication. IEICE Trans. Inf. Syst. 100-D(3): 531-536 (2017) - 2014
- [j4]Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi:
Circuit Description and Design Flow of Superconducting SFQ Logic Circuits. IEICE Trans. Electron. 97-C(3): 149-156 (2014) - 2013
- [j3]Nobutaka Kito, Naofumi Takagi:
Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication. IEICE Trans. Inf. Syst. 96-D(9): 1962-1970 (2013) - 2012
- [j2]Nobutaka Kito, Shinichi Fujii, Naofumi Takagi:
A C-Testable Multiple-Block Carry Select Adder. IEICE Trans. Inf. Syst. 95-D(4): 1084-1092 (2012) - 2010
- [j1]Nobutaka Kito, Kensuke Hanai, Naofumi Takagi:
A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier. IEICE Trans. Inf. Syst. 93-D(10): 2783-2791 (2010)
2000 – 2009
- 2008
- [c1]Nobutaka Kito, Naofumi Takagi:
Level-Testability of Multi-operand Adders. ATS 2008: 260-262
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