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ORCIDDavid Esseni
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2020 – today
- 2024
[j7]Riccardo Fontanini
, Alessandro Pilotto, David Esseni, Mirko Loghi:
Reducing the spike rate of deep spiking neural networks based on time-encoding. Neuromorph. Comput. Eng. 4(3): 34004 (2024)- 2023
- [c21]Suzanne Lancaster, Mattia Segatto, Cláudia Silva, Benjamin Max, Thomas Mikolajick, David Esseni, Francesco Driussi, Stefan Slesazeck:
Reducing the tunneling barrier thickness of bilayer ferroelectric tunnel junctions with metallic electrodes. DRC 2023: 1-2 - [c20]Marco Massarotto, Stefano Saggini, Mirko Loghi, David Esseni:
Adiabatic Spiking Neurons and Synapses for Ultra-Low Energy Neuromorphic Computing. ICECS 2023: 1-4 - [i5]Daniel Lizzit, Thomas Bernardi, David Esseni:
Multi-level Operation of FeFETs Memristors: the Crucial Role of Three Dimensional Effects. CoRR abs/2308.13912 (2023) - [i4]David Esseni, Francesco Driussi, Daniel Lizzit, Marco Massarotto, Mattia Segatto:
Modelling and Simulations of Ferroelectric Materials and Ferroelectric-Based Nanoelectronic Devices. CoRR abs/2311.03864 (2023) - 2022
- [c19]Mattia Segatto, Marco Massarotto, Suzanne Lancaster, Quang T. Duong, Antonio Affanni, Riccardo Fontanini, Francesco Driussi, Daniel Lizzit, Thomas Mikolajick, Stefan Slesazeck, David Esseni:
Polarization switching and AC small-signal capacitance in Ferroelectric Tunnel Junctions. ESSDERC 2022: 340-343 - [c18]Daniel Lizzit, Thomas Bernardi, David Esseni:
Multi-level Operation of FeFETs Memristors: the Crucial Role of Three Dimensional Effects. ESSDERC 2022: 344-347 - [c17]Riccardo Fontanini, David Esseni, Mirko Loghi:
Reducing the Spike Rate in Deep Spiking Neural Networks. ICONS 2022: 8:1-8:8 - [i3]Daniel Lizzit, David Esseni:
Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation. CoRR abs/2209.05133 (2022) - 2021
- [c16]Daniel Lizzit, David Esseni:
Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation. ESSDERC 2021: 215-218 - [c15]Riccardo Fontanini, Justine Barbot, Mattia Segatto, Suzanne Lancaster, Quang T. Duong, Francesco Driussi, Laurent Grenouillet, François Triozon, Jean Coignus, Thomas Mikolajick, Stefan Slesazeck, David Esseni:
Polarization switching and interface charges in BEOL compatible Ferroelectric Tunnel Junctions. ESSDERC 2021: 255-258 - [i2]Riccardo Fontanini, Marco Massarotto, Ruben Specogna, Francesco Driussi, Mirko Loghi, David Esseni:
Modelling and design of FTJs as high reading-impedance synaptic devices. CoRR abs/2105.00752 (2021) - [i1]David Esseni, Riccardo Fontanini, Daniel Lizzit, Marco Massarotto, Francesco Driussi, Mirko Loghi:
Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies. CoRR abs/2105.00864 (2021)
2010 – 2019
- 2016
- [c14]Martin Rau, Troels Markussen, Enrico Caruso, David Esseni, Elena Gnani, Antonio Gnudi, Petr A. Khomyakov, Mathieu Luisier, Patrik Osgnach, Pierpaolo Palestri, Susanna Reggiani, Andreas Schenk, Luca Selmi, Kurt Stokbro:
Performance study of strained III-V materials for ultra-thin body transistor applications. ESSDERC 2016: 184-187 - [c13]Tommaso Rollo, David Esseni:
Supersteep retrograde doping in ferroelectric MOSFETs for sub-60mV/dec subthreshold swing. ESSDERC 2016: 360-363 - 2015
- [c12]O. Badami, Enrico Caruso, Daniel Lizzit, David Esseni, Pierpaolo Palestri, Luca Selmi:
Improved surface roughness modeling and mobility projections in thin film MOSFETs. ESSDERC 2015: 306-309 - [c11]Manouchehr Hosseini, Mohammad Elahi, Ebrahim Asl Soleimani, Mahdi Pourfath, David Esseni:
Strain engineering of single-layer MoS2. ESSDERC 2015: 314-317 - [c10]Pierpaolo Palestri, Enrico Caruso, Francesco Driussi, David Esseni, Daniel Lizzit, Patrik Osgnach, Stefano Venica, Luca Selmi:
State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors. MIPRO 2015: 1-8 - 2014
- [j6]David Esseni, Manuel Guglielmini, Bernard Kapidani, Tommaso Rollo, Massimo Alioto:
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2488-2498 (2014) - [j5]Massimo Alioto, David Esseni:
Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2499-2512 (2014) - [c9]Sebastiano Strangio, Pierpaolo Palestri, David Esseni, Luca Selmi, Felice Crupi:
Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires. ESSDERC 2014: 282-285 - [c8]David Esseni, Massimo Alioto:
Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits. NEWCAS 2014: 321-324 - [c7]Massimo Alioto, David Esseni:
Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits. SBCCI 2014: 32:1-32:6 - 2012
- [j4]Davide Baccarin, David Esseni, Massimo Alioto:
Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1467-1472 (2012) - [c6]Daniel Lizzit, Pierpaolo Palestri, David Esseni, Francesco Conzatti, Luca Selmi:
A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs. ESSDERC 2012: 322-325 - 2011
- [c5]Davide Baccarin, David Esseni, Massimo Alioto:
A novel back-biasing low-leakage technique for FinFET forced stacks. ISCAS 2011: 2079-2082 - 2010
- [j3]Michele Nocente, Donald Fontanelli, Pierpaolo Palestri, Roberto Nonis, David Esseni, Luca Selmi:
A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators. Int. J. Circuit Theory Appl. 38(6): 607-629 (2010) - [j2]Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi:
Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 232-245 (2010)
2000 – 2009
- 2009
- [j1]Davide Ponton, Pierpaolo Palestri, David Esseni, Luca Selmi, Marc Tiebout, Bertrand Parvais, Domagoj Siprak, Gerhard Knoblinger:
Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(5): 920-932 (2009) - 2008
- [c4]Davide Ponton, Pierpaolo Palestri, David Esseni, Luca Selmi, Marc Tiebout, Bertrand Parvais, Gerhard Knoblinger:
Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET. ISCAS 2008: 2701-2704 - [c3]Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi:
Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction. PATMOS 2008: 31-41 - 2007
- [c2]Enrico Sangiorgi, Pierpaolo Palestri, David Esseni, Claudio Fiegna, Luca Selmi:
The Monte Carlo approach to transport modeling in deca-nanometer MOSFETs. ESSCIRC 2007: 48-57 - 2001
- [c1]Roberto Versari, David Esseni, Gianluca Falavigna, Massimo Lanzoni, Bruno Riccò:
Optimized programming of multilevel flash EEPROMs. ICECS 2001: 945-948
Coauthor Index
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