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ORCIDAjay N. Bhoj
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2010 – 2019
- 2016
[c5]Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha:
Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. VLSID 2016: 300-305- 2015
- [j7]Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh:
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 534-543 (2015) - [j6]Debajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha:
Design of Efficient Content Addressable Memories in High-Performance FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 963-967 (2015) - 2014
- [j5]Ajay N. Bhoj, Niraj K. Jha:
Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 548-561 (2014) - 2013
- [j4]Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha:
Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 47-58 (2013) - [j3]Ajay N. Bhoj, Niraj K. Jha:
Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 1975-1988 (2013) - [j2]Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha:
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2094-2105 (2013) - 2011
- [c4]Ajay N. Bhoj, Niraj K. Jha:
Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology. ISQED 2011: 695-702 - 2010
- [j1]Ajay N. Bhoj, Niraj K. Jha:
Gated-diode FinFET DRAMs: Device and circuit design-considerations. ACM J. Emerg. Technol. Comput. Syst. 6(4): 12:1-12:32 (2010) - [c3]Prateek Mishra, Ajay N. Bhoj, Niraj K. Jha:
Die-level leakage power analysis of FinFET circuits considering process variations. ISQED 2010: 347-355 - [c2]Muzaffer O. Simsir, Ajay N. Bhoj, Niraj K. Jha:
Fault modeling for FinFET circuits. NANOARCH 2010: 41-46
2000 – 2009
- 2009
- [c1]Ajay N. Bhoj, Niraj K. Jha:
Pragmatic design of gated-diode FinFET DRAMs. ICCD 2009: 390-397
Coauthor Index
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