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2010 – 2019
- 2013
[j4]Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris:
Scalable matrix decompositions with multiple cores on FPGAs. Microprocess. Microsystems 37(8-B): 887-898 (2013)- 2012
- [j3]Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris:
Accelerating Matrix Operations with Improved Deeply Pipelined Vector Reduction. IEEE Trans. Parallel Distributed Syst. 23(2): 202-210 (2012) - 2011
- [c8]Yi-Gang Tai, Kleanthis Psarris, Chia-Tien Dan Lo:
Synthesizing Tiled Matrix Decomposition on FPGAs. FPL 2011: 464-469 - 2010
- [c7]Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris:
Multiple data set reduction on FPGAs. FPT 2010: 45-52
2000 – 2009
- 2009
- [j2]Chia-Tien Dan Lo, Yi-Gang Tai:
Space Optimization on Counters for FPGA-Based Perl Compatible Regular Expressions. ACM Trans. Reconfigurable Technol. Syst. 2(4): 23:1-23:18 (2009) - [c6]Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris:
An Improved Reduction Algorithm With Deeply Pipelined Operators. SMC 2009: 3060-3065 - 2008
- [c5]Chia-Tien Dan Lo, Yi-Gang Tai:
Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs. ARC 2008: 51-62 - [c4]Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris:
Accelerating matrix decomposition with replications. IPDPS 2008: 1-8 - [c3]Chia-Tien Dan Lo, Yi-Gang Tai, Kleanthis Psarris:
Hardware implementation for network intrusion detection rules with regular expression support. SAC 2008: 1535-1539 - 2007
- [c2]Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris:
Applying Out-of-Core QR Decomposition Algorithms on FPGA-Based Systems. FPL 2007: 86-91 - 2006
- [c1]Chia-Tien Dan Lo, Yi-Gang Tai, Kleanthis Psarris, Wen-Jyi Hwang:
Super fast hardware string matching. FPT 2006: 385-388 - 2002
- [j1]Kuo-Chih Chu, Yi-Gang Tai, Wei-Tsong Lee, Pau-Choo Chung:
A novel mechanism for providing service differentiation over CATV network. Comput. Commun. 25(13): 1214-1229 (2002)
Coauthor Index
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