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ORCIDV. S. Kanchana Bhaaskaran
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- affiliation: Vellore Institute of Technology Chennai, India
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2020 – today
- 2024
[j19]Hemavathy Sriramulu
, J. Kokila, V. S. Kanchana Bhaaskaran:
Adaptive PUF design to authenticate and evaluate heterogeneous IPs in edge computing. J. Supercomput. 80(16): 24689-24717 (2024)- 2023
- [j18]Hemavathy Sriramulu, V. S. Kanchana Bhaaskaran:
Arbiter PUF - A Review of Design, Composition, and Security Aspects. IEEE Access 11: 33979-34004 (2023) - 2022
- [j17]Hemavathy Sriramulu, Kanchana Bhaaskaran Vettuvanam Somasundaram:
Design and Analysis of Secure Quasi-Adiabatic Tristate Physical Unclonable Function. IEEE Consumer Electron. Mag. 11(4): 98-104 (2022) - [j16]Prathiba Ashok, Suyash Vardhan Srivathshav, E. Ramkumar, P. Rajkamal, V. S. Kanchana Bhaaskaran:
Lightweight VLSI Architectures for Image Encryption Applications. Int. J. Inf. Secur. Priv. 16(1): 1-23 (2022) - 2021
- [c13]Hemavathy Sriramulu, V. S. Kanchana Bhaaskaran:
Double Edge-Triggered Tristate Flip-Flop Physical Unclonable Function for Secure IoT Ecosystem. iSES 2021: 44-47 - 2020
- [j15]Bhuvana B. P., V. S. Kanchana Bhaaskaran:
Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures. J. Circuits Syst. Comput. 29(1): 2050016:1-2050016:23 (2020) - [c12]Hemavathy Sriramulu, V. S. Kanchana Bhaaskaran:
Design and Analysis of Secure Quasi-Adiabatic Tristate Physical Unclonable Function. iSES 2020: 109-114 - [c11]E. Ramkumar, D. Gracin, P. Rajkamal, Bhuvana B. P., V. S. Kanchana Bhaaskaran:
Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS). iSES 2020: 281-284 - [c10]Keshav Govindarajan, V. S. Kanchana Bhaaskaran:
Borrow Select Subtractor for Low Power and Area Efficiency. ISVLSI 2020: 518-523
2010 – 2019
- 2019
- [j14]A. Anita Angeline, V. S. Kanchana Bhaaskaran:
Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit. IET Circuits Devices Syst. 13(8): 1134-1141 (2019) - [j13]Prathiba Ashok, Kanchana Bhaaskaran Vettuvanam Somasundaram:
Charge balancing symmetric pre-resolve adiabatic logic against power analysis attacks. IET Inf. Secur. 13(6): 692-702 (2019) - [j12]Prathiba Ashok, Kanchana Bhaaskaran Vettuvanam Somasundaram:
Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems. Integr. 69: 266-278 (2019) - [j11]Bhuvana B. P., V. S. Kanchana Bhaaskaran:
Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications. Microelectron. J. 92 (2019) - [c9]Jayashree K. G, Lois Priscilla S, Bhuvana B. P., V. S. Kanchana Bhaaskaran:
Design and Analysis of FinFET Based CSCPAL Low Power Adder. iSES 2019: 139-144 - 2018
- [j10]Prathiba Ashok, Kanchana Bhaaskaran Vettuvanam Somasundaram:
Lightweight S-Box Architecture for Secure Internet of Things. Inf. 9(1): 13 (2018) - [j9]P. Sasipriya, V. S. Kanchana Bhaaskaran:
Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL). J. Circuits Syst. Comput. 27(4): 1850052:1-1850052:22 (2018) - [j8]P. Sasipriya, Kanchana Bhaaskaran Vettuvanam Somasundaram:
Design and Analysis of Clocked CMOS Differential Adiabatic Logic (CCDAL) for Low Power. J. Low Power Electron. 14(4): 548-557 (2018) - [c8]V. S. Kanchana Bhaaskaran:
Energy Recovery Circuit Design for Low Power VLSI. iSES 2018: 11-16 - [c7]Bhuvana B. P., V. S. Kanchana Bhaaskaran:
Positive Feedback Symmetric Adiabatic Logic Against Differential Power Attack. VLSID 2018: 149-154 - 2017
- [j7]Saroja S. Bhusare, V. S. Kanchana Bhaaskaran:
Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique. J. Circuits Syst. Comput. 26(5): 1750079:1-1750079:12 (2017) - [j6]N. Poornima, V. S. Kanchana Bhaaskaran:
Design and Implementation of 32-Bit High Valency Jackson Adders. J. Circuits Syst. Comput. 26(7): 1750123:1-1750123:18 (2017) - 2016
- [j5]Jennifer Judy Dominic Jawahar, Supreeth Mysore Shivananda Murthy, Kanchana Bhaaskaran Vettuvanam Somasundaram:
Self-gated resonant-clocked flip-flop optimised for power efficiency and signal integrity. IET Circuits Devices Syst. 10(2): 94-103 (2016) - [j4]Kore Sagar Dattatraya, Ritesh Belgudri, Ramdas Bhanudas Khaladkar, V. S. Kanchana Bhaaskaran:
Low Power, High Speed and Area Efficient Binary Count Multiplier. J. Circuits Syst. Comput. 25(4): 1650027:1-1650027:17 (2016) - 2015
- [c6]P. Sasipriya, V. S. Kanchana Bhaaskaran:
Two phase sinusoidal power clocked quasi-static adiabatic logic families. IC3 2015: 503-508 - [c5]Deeksha Anandani, Anurag Kumar, V. S. Kanchana Bhaaskaran:
Gating techniques for 6T SRAM cell using different modes of FinFET. ICACCI 2015: 483-487 - 2014
- [c4]Dalal Rutwik Kishor, V. S. Kanchana Bhaaskaran:
Low power divider using vedic mathematics. ICACCI 2014: 575-580 - [c3]M. Divya, Ritesh Belgudri, V. S. Kanchana Bhaaskaran:
Design and analysis of program counter using finite state machine and incrementer based logic. ICACCI 2014: 581-587 - [c2]Hardik Sangani, Tanay M. Modi, V. S. Kanchana Bhaaskaran:
Low power vedic multiplier using energy recovery logic. ICACCI 2014: 640-644 - 2012
- [j3]V. S. Kanchana Bhaaskaran, J. P. Raina:
Pre-Resolve and Sense Adiabatic Logic for 100 kHz to 500 MHz Frequency Classes. J. Circuits Syst. Comput. 21(5) (2012) - 2010
- [j2]V. S. Kanchana Bhaaskaran, J. P. Raina:
Two-Phase sinusoidal Power-Clocked Quasi-Adiabatic Logic Circuits. J. Circuits Syst. Comput. 19(2): 335-347 (2010)
2000 – 2009
- 2008
- [j1]V. S. Kanchana Bhaaskaran, J. P. Raina:
Differential Cascode Adiabatic Logic Structure for Low Power. J. Low Power Electron. 4(2): 178-190 (2008) - 2006
- [c1]V. S. Kanchana Bhaaskaran, S. Salivahanan, D. S. Emmanuel:
Semi-Custom Design of Adiabatic Adder Circuits. VLSI Design 2006: 745-748
Coauthor Index
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