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ORCIDFernando M. Gonçalves
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2010 – 2019
- 2019
[c25]Luís Fiolhais, Fernando M. Gonçalves
, Rui Policarpo Duarte, Mário P. Véstias, José T. de Sousa:
Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. ISCAS 2019: 1-5- 2016
- [j7]João M. P. Cardoso, José Gabriel F. Coutinho, Tiago Carvalho, Pedro C. Diniz, Zlatko Petrov, Wayne Luk, Fernando M. Gonçalves:
Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach. Softw. Pract. Exp. 46(2): 251-287 (2016) - 2014
- [c24]Razvan Nane, Vlad Mihai Sima, Cuong Pham-Quoc, Fernando M. Gonçalves, Koen Bertels:
High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain. EUC 2014: 138-145 - 2012
- [c23]João M. P. Cardoso, Tiago Carvalho, João Teixeira, Pedro C. Diniz, Fernando M. Gonçalves, Zlatko Petrov:
Hardware/software specialization through aspects: The LARA approach. ICSAMOS 2012: 260-267
2000 – 2009
- 2009
- [c22]Edgar F. M. Albuquerque, Vasco Bexiga, Ricardo Bugalho, Bruno Carriço, Cláudia S. Ferreira, Miguel Ferreira, Joaquim Godinho, Fernando M. Gonçalves, Carlos Leong, Pedro Lousã, Pedro Machado, Rui Moura, Pedro Neves, Catarina Ortigão, Fernando Piedade, João F. Pinheiro, P. Relvas, Angelo Rivetti, Pedro Miguel Rodrigues, José C. Silva, Manuel M. Silva, Isabel C. Teixeira, João Paulo Teixeira, Andreia Trindade, João Varela:
On-Detector Electronics of the Clear PEM Scanner. BIODEVICES 2009: 355-358 - 2005
- [c21]Victor Gonçalves, José T. de Sousa, Fernando M. Gonçalves:
A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. FPL 2005: 481-486 - 2003
- [c20]Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. IOLTS 2003: 164-165 - 2002
- [j6]Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage. J. Electron. Test. 18(2): 179-187 (2002) - [j5]Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System. J. Electron. Test. 18(3): 285-294 (2002) - [c19]Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. DFT 2002: 216-224 - [c18]José T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura:
DARP - A Digital Audio Reconfigurable Processor. FPL 2002: 556-566 - 2001
- [j4]Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems. J. Electron. Test. 17(3-4): 311-319 (2001) - [c17]Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
RTL design validation, DFT and test pattern generation for high defects coverage. ETW 2001: 99-105 - [c16]Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. IOLTW 2001: 197-201 - [c15]Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. ITC 2001: 377-385 - 2000
- [c14]Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
RTL-based functional test generation for high defects coverage in digital SOCs. ETW 2000: 99-104
1990 – 1999
- 1999
- [j3]Fernando M. Gonçalves, João Paulo Teixeira:
Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems. J. Electron. Test. 15(1-2): 41-52 (1999) - [c13]Fernando M. Gonçalves, João Paulo Teixeira:
Teaching Microelectronic-Based Integrated Systems Design and Test. MSE 1999: 65-66 - [c12]Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. VTS 1999: 326-332 - 1998
- [c11]Marcelino B. Santos, Fernando M. Gonçalves, Michael J. Ohletz, João Paulo Teixeira:
Defect-oriented testing of analogue and mixed signal ICs. ICECS 1998: 419-424 - [c10]Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Defect-oriented test quality assessment using fault sampling and simulation. ITC 1998: 35-42 - [c9]Fernando M. Gonçalves, João Paulo Teixeira:
Sampling Techniques of Non-Equally Probable Faults in VLSI System. VTS 1998: 283-288 - 1997
- [c8]Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. DFT 1997: 29-37 - 1996
- [j2]José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams:
Defect level evaluation in an IC design environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1286-1293 (1996) - [c7]Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
Integrated Approach for Circuit and Fault Extraction of VLSI Circuits. DFT 1996: 96-104 - 1994
- [c6]A. P. Casimiro, Fernando M. Gonçalves, João Paulo Teixeira, Marcelino B. Santos:
On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits. DFT 1994: 263-270 - [c5]José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams:
Fault Modeling and Defect Level Projections in Digital ICs. EDAC-ETC-EUROASIC 1994: 436-442 - [c4]Mario Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. ITC 1994: 720-728 - 1992
- [c3]M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
Physical DFT for High Coverage of Realistic Faults. ITC 1992: 642-651 - 1991
- [j1]João Paulo Teixeira, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves:
A methodology for testability enhancement at layout level. J. Electron. Test. 1(4): 287-299 (1991) - [c2]José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira:
IC Defects-Based Testability Analysis. ITC 1991: 500-509 - 1990
- [c1]João Paulo Teixeira, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves, R. Crespo:
A strategy for testability enhancement at layout level. EURO-DAC 1990: 413-417
Coauthor Index
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