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2020 – today
- 2023
[j5]Flavio Ponzina
, Marco Rios, Alexandre Levisse, Giovanni Ansaloni, David Atienza:
Overflow-free Compute Memories for Edge AI Acceleration. ACM Trans. Embed. Comput. Syst. 22(5s): 121:1-121:23 (2023)- [j4]Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza:
Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. IEEE Trans. Emerg. Top. Comput. 11(2): 358-372 (2023) - [c8]Grégoire Eggermann, Marco Rios, Giovanni Ansaloni, Sani R. Nassif, David Atienza:
A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication. VLSI-SoC 2023: 1-6 - 2022
- [j3]Flavio Ponzina, Simone Machetti, Marco Rios, Benoît Walter Denkinger, Alexandre Levisse, Giovanni Ansaloni, Miguel Peón Quirós, David Atienza:
A Hardware/Software Co-Design Vision for Deep Learning at the Edge. IEEE Micro 42(6): 48-54 (2022) - [c7]Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza:
Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge. ACM Great Lakes Symposium on VLSI 2022: 249-254 - [i1]Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza:
Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. CoRR abs/2209.06108 (2022) - 2021
- [c6]Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza:
Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing. DATE 2021: 1881-1886 - [c5]Flavio Ponzina, Marco Rios, Giovanni Ansaloni, Alexandre Levisse, David Atienza:
A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs. ISVLSI 2021: 164-169 - 2020
- [j2]Alexandre Levisse, Marc Bocquet, Marco Rios, Mouhamad Alayan, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, David Atienza, Jean-Michel Portal:
Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations. IEEE Access 8: 109297-109308 (2020) - [j1]William Andrew Simon, Yasir Mahmood Qureshi, Marco Rios, Alexandre Levisse, Marina Zapater, David Atienza:
BLADE: An in-Cache Computing Architecture for Edge Devices. IEEE Trans. Computers 69(9): 1349-1363 (2020) - [c4]Shikhar Tuli, Marco Rios, Alexandre Levisse, David Atienza:
RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures. ASP-DAC 2020: 181-186 - [c3]Alexandre Levisse, Marco Rios, Miguel Peón Quirós, David Atienza:
Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems. ICASSP 2020: 1549-1552
2010 – 2019
- 2019
- [c2]Alexandre Levisse, Marco Rios, William Andrew Simon, Pierre-Emmanuel Gaillardon, David Atienza:
Functionality Enhanced Memories for Edge-AI Embedded Systems. NVMTS 2019: 1-4 - [c1]Marco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza:
An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication. VLSI-SoC 2019: 34-39
Coauthor Index
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