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ORCIDUday Dasgupta
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2010 – 2019
- 2016
[c7]Uday Dasgupta:
Low voltage 2-stage and 3-stage push-pull output amplifiers in 65-nm CMOS technology. ISIC 2016: 1-4- 2015
- [j2]Xiao Liang Tan, Pak Kwong Chan, Uday Dasgupta:
A Sub-1-V 65-nm MOS Threshold Monitoring-Based Voltage Reference. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2317-2321 (2015) - 2014
- [j1]Xiao Liang Tan, Sau Siong Chong, Pak Kwong Chan, Uday Dasgupta:
A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF-10 nF Capacitive Load. IEEE J. Solid State Circuits 49(11): 2658-2672 (2014) - [c6]Xiao Liang Tan, Pak Kwong Chan, Uday Dasgupta:
An asynchronous sub-two-step quantizer for continuous-time sigma-delta modulators. ISCAS 2014: 710-713 - [c5]Uday Dasgupta, Geok Teng Ong, Junmin Cao, Soong Lin Chew:
A versatile three-stage operational amplifier with Second-stage Bypass Compensation. ISIC 2014: 232-235 - [c4]Wee Liang Lien, Tieng Yi Choke, Ying Chow Tan, Ming Kong, Eng-Chuan Low, Dan Ping Li, Liming Jin, Huajiang Zhang, Chin Heng Leow, Soong Lin Chew, Uday Dasgupta, Chee-Hong Yong, Tianbao Gao, Geok Teng Ong, Wee Guan Tan, Weimin Shu, Chee-Lee Heng, Osama Shana'a
:
9.1 A self-calibrating NFC SoC with a triple-mode reconfigurable PLL and a single-path PICC-PCD receiver in 0.11μm CMOS. ISSCC 2014: 158-159
2000 – 2009
- 2009
- [c3]Uday Dasgupta, Alexander Tanzil:
High Power-supply Rejection Low Drop-out Regulator. ISCAS 2009: 824-827 - 2003
- [c2]Uday Dasgupta, Yong Ping Xu:
Effects of resistive loading on unity gain frequency of two-stage CMOS operational amplifiers. ISCAS (1) 2003: 361-364
1990 – 1999
- 1999
- [c1]X. W. Zhang, M. F. Li, Uday Dasgupta:
Low-voltage linear OTA with rail-to-rail differential mode input signal capability. ICECS 1999: 603-606
Coauthor Index
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