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2020 – today
- 2024
[j34]Kunyue Li
, Zhengji Zhao, Qixuan Cai, Qin Wang, Naifeng Jing, Zhigang Mao, Jianfei Jiang:
A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance. Expert Syst. Appl. 249: 123828 (2024)- [j33]Zihan Zhang, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing:
3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 176-188 (2024) - [j32]Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing:
DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1163-1176 (2024) - [j31]Weidong Yang, Yuqing Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng:
RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 2854-2867 (2024) - [c77]Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing:
SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration. ASPDAC 2024: 225-230 - [c76]Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing:
Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture. ASPDAC 2024: 460-465 - [c75]Zhuoran Song, Chunyu Qi, Fangxin Liu, Naifeng Jing, Xiaoyao Liang:
CMC: Video Transformer Acceleration via CODEC Assisted Matrix Condensing. ASPLOS (2) 2024: 201-215 - [c74]Lei Xu, Zhiwen Mo, Qin Wang, Jianfei Jiang, Naifeng Jing:
Enabling Multiple Tensor-wise Operator Fusion for Transformer Models on Spatial Accelerators. DAC 2024: 232:1-232:6 - [c73]Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Naifeng Jing, Li Jiang, Xiaoyao Liang:
Watt: A Write-Optimized RRAM-Based Accelerator for Attention. Euro-Par (2) 2024: 107-120 - [c72]Duo Yu, Ang Li, Naifeng Jing, Jianfei Jiang, Weiguang Sheng, Qin Wang:
VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks. ACM Great Lakes Symposium on VLSI 2024: 357-363 - [c71]Yilong Zhao, Mingyu Gao, Fangxin Liu, Yiwei Hu, Zongwu Wang, Han Lin, Jin Li, He Xian, Hanlin Dong, Tao Yang, Naifeng Jing, Xiaoyao Liang, Li Jiang:
UM-PIM: DRAM-based PIM with Uniform & Shared Memory Space. ISCA 2024: 644-659 - [c70]Lin Xie, Zizheng Dong, Jialei Sun, Sai Gao, Shuaipeng Li, Naifeng Jing, Qin Wang, Jianfei Jiang:
A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction. ISCAS 2024: 1-5 - [c69]Zelong Yuan, Siwei Yuan, Pengyu Liu, Chen Yin, Lei Xu, Weiguang Sheng, Naifeng Jing:
A Flexible and High-Precision Activation Function Unit Based on Equi-Error Partitioning Algorithm. ISCAS 2024: 1-5 - [i7]Zhiwen Mo, Lei Wang, Jianyu Wei, Zhichen Zeng, Shijie Cao, Lingxiao Ma, Naifeng Jing, Ting Cao, Jilong Xue, Fan Yang, Mao Yang:
LUT Tensor Core: Lookup Table Enables Efficient Low-Bit LLM Inference Acceleration. CoRR abs/2408.06003 (2024) - 2023
- [j30]Naifeng Jing, Zihan Zhang, Yongshuai Sun, Pengyu Liu, Liyan Chen, Qin Wang, Jianfei Jiang:
Exploiting bit sparsity in both activation and weight in neural networks accelerators. Integr. 88: 400-409 (2023) - [j29]Chen Yin, Naifeng Jing, Jianfei Jiang, Qin Wang, Zhigang Mao:
A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 874-886 (2023) - [j28]Zhuoran Song, Heng Lu, Li Jiang, Naifeng Jing, Xiaoyao Liang:
Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2238-2251 (2023) - [j27]Zhuoran Song, Naifeng Jing, Xiaoyao Liang:
E2-VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition. ACM Trans. Design Autom. Electr. Syst. 28(1): 10:1-10:21 (2023) - [j26]Zhuoran Song, Wanzhen Liu, Tao Yang, Fangxin Liu, Naifeng Jing, Xiaoyao Liang:
A Point Cloud Video Recognition Acceleration Framework Based on Tempo-Spatial Information. IEEE Trans. Parallel Distributed Syst. 34(12): 3224-3237 (2023) - [c68]Zhuoran Song, Naifeng Jing, Xiaoyao Liang:
PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation. ACM TUR-C 2023: 49-50 - [c67]Zhuo Chen, Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Naifeng Jing:
ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator. ASICON 2023: 1-4 - [c66]Jianing Gao, Lingyi Liu, Qin Wang, Naifeng Jing, Jianfei Jiang:
High-Performance Genomic Analysis Heterogeneous System Using OpenCL. ASICON 2023: 1-4 - [c65]Jianing Gao, Qiming Shao, Fangyu Deng, Qin Wang, Naifeng Jing, Jianfei Jiang:
An NoC-based CNN Accelerator for Edge Computing. ASICON 2023: 1-4 - [c64]Yuqing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang, Zhigang Mao, Weiguang Sheng:
An Efficient near-Bank Processing Architecture for Personalized Recommendation System. ASP-DAC 2023: 122-127 - [c63]Xiaolong Lin, Gang Li, Zizhao Liu, Yadong Liu, Fan Zhang, Zhuoran Song, Naifeng Jing, Xiaoyao Liang:
AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity. DAC 2023: 1-6 - [c62]Zhuoran Song, Heng Lu, Gang Li, Li Jiang, Naifeng Jing, Xiaoyao Liang:
PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation. DATE 2023: 1-6 - [c61]Pengyu Liu, Zihan Zhang, Chen Yin, Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing:
Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture. FPL 2023: 116-122 - [c60]Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Weiguang Sheng, Ang Li, Qin Wang:
ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors. ICCD 2023: 54-61 - [c59]Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Li Jiang, Naifeng Jing, Xiaoyao Liang:
HyAcc: A Hybrid CAM-MAC RRAM-based Accelerator for Recommendation Model. ICCD 2023: 375-382 - [c58]Haifeng Xiang, Naifeng Jing, Jianfei Jiang, Hongbo Guo, Weiguang Sheng, Zhigang Mao, Qin Wang:
RTMDet-R2: An Improved Real-Time Rotated Object Detector. PRCV (12) 2023: 352-364 - 2022
- [j25]Guochao Deng, Qin Wang, Jianfei Jiang, Qirun Hong, Naifeng Jing, Weiguang Sheng, Zhigang Mao:
A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images. IEEE Geosci. Remote. Sens. Lett. 19: 1-5 (2022) - [j24]Taozhong Li, Naifeng Jing, Zhigang Mao, Yiran Chen:
A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1842-1854 (2022) - [j23]Zihan Zhang, Jianfei Jiang, Yongxin Zhu, Qin Wang, Zhigang Mao, Naifeng Jing:
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2094-2106 (2022) - [j22]Taozhong Li, Naifeng Jing, Jianfei Jiang, Qin Wang, Zhigang Mao, Yiran Chen:
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator. ACM Trans. Design Autom. Electr. Syst. 27(6): 57:1-57:22 (2022) - [j21]Shengzhao Li, Qin Wang, Jianfei Jiang, Weiguang Sheng, Naifeng Jing, Zhigang Mao:
An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1587-1600 (2022) - [c57]Mengyu Guo, Zihan Zhang, Jianfei Jiang, Qin Wang, Naifeng Jing:
Boosting ReRAM-based DNN by Row Activation Oversubscription. ASP-DAC 2022: 604-609 - [c56]Zhuoran Song, Zhongkai Yu, Naifeng Jing, Xiaoyao Liang:
E2SR: an end-to-end video CODEC assisted system for super resolution acceleration. DAC 2022: 229-234 - [c55]Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang:
EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks. DAC 2022: 259-264 - [c54]Xing Li, Rachata Ausavarungnirun, Xiao Liu, Xueyuan Liu, Xuan Zhang, Heng Lu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang:
Gzippo: Highly-Compact Processing-in-Memory Graph Accelerator Alleviating Sparsity and Redundancy. ICCAD 2022: 115:1-115:9 - [c53]Heng Lu, Zhuoran Song, Xing Li, Naifeng Jing, Xiaoyao Liang:
GCNTrain: A Unified and Efficient Accelerator for Graph Convolutional Neural Network Training. ICCD 2022: 730-737 - [c52]Gang Li, Weixiang Xu, Zhuoran Song, Naifeng Jing, Jian Cheng, Xiaoyao Liang:
Ristretto: An Atomized Processing Architecture for Sparsity-Condensed Stream Flow in CNN. MICRO 2022: 1434-1450 - [i6]Zhuoran Song, Yihong Xu, Zhezhi He, Li Jiang, Naifeng Jing, Xiaoyao Liang:
CP-ViT: Cascade Vision Transformer Pruning via Progressive Sparsity Prediction. CoRR abs/2203.04570 (2022) - [i5]Zhuoran Song, Yihong Xu, Han Li, Naifeng Jing, Xiaoyao Liang, Li Jiang:
DNN Training Acceleration via Exploring GPGPU Friendly Sparsity. CoRR abs/2203.05705 (2022) - [i4]Yilong Zhao, Li Jiang, Mingyu Gao, Naifeng Jing, Chengyang Gu, Qidong Tang, Fangxin Liu, Tao Yang, Xiaoyao Liang:
RePAST: A ReRAM-based PIM Accelerator for Second-order Training of DNN. CoRR abs/2210.15255 (2022) - 2021
- [j20]Zhuoran Song, Yanan Sun, Lerong Chen, Tianjian Li, Naifeng Jing, Xiaoyao Liang, Li Jiang:
ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 129-142 (2021) - [j19]Zhuojun Liang, Dongxu Lv, Chao Cui, Hai-Bao Chen, Weifeng He, Weiguang Sheng, Naifeng Jing, Zhigang Mao, Guanghui He:
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 307-320 (2021) - [c51]Yongshuai Sun, Mengyu Guo, Dacheng Liang, Shan Tang, Naifeng Jing:
Exploiting Dynamic Bit Sparsity in Activation for Deep Neural Network Acceleration. ASICON 2021: 1-4 - [c50]Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, Naifeng Jing:
A Mapping Method for Reconfigurable Array based on Decoupled DataFlow. BigDataSecurity 2021: 180-185 - [c49]Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing:
Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. DATE 2021: 1394-1399 - [c48]Yilong Zhao, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang:
Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication. ACM Great Lakes Symposium on VLSI 2021: 15-20 - [c47]Yongquan Shi, Yongshuai Sun, Jianfei Jiang, Guanghui He, Qin Wang, Naifeng Jing:
Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator. ISCAS 2021: 1-5 - [c46]Feiyang Wu, Zhuoran Song, Jing Ke, Li Jiang, Naifeng Jing, Xiaoyao Liang:
PIPArch: Programmable Image Processing Architecture Using Sliding Array. ISPA/BDCloud/SocialCom/SustainCom 2021: 73-80 - [i3]Fangxin Liu, Wenbo Zhao, Yilong Zhao, Zongwu Wang, Tao Yang, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang:
SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network. CoRR abs/2103.01705 (2021) - 2020
- [j18]Yijia Zhang, Weiguang Sheng, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao:
Priority Branches for Ship Detection in Optical Remote Sensing Images. Remote. Sens. 12(7): 1196 (2020) - [j17]Guanghui He, Sijie Zheng, Naifeng Jing:
A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 28(10): 2134-2145 (2020) - [c45]Jing Ke, Changchang Liu, Yizhou Lu, Naifeng Jing, Xiaoyao Liang, Fusong Jiang:
FIMIL : A high-throughput deep learning model for abnormality detection with weak annotation in microscopy images. ACSW 2020: 34:1-34:6 - [c44]Jing Ke, Yiqing Shen, Yi Guo, Jason D. Wright, Naifeng Jing, Xiaoyao Liang:
A High-Throughput Tumor Location System with Deep Learning for Colorectal Cancer Histopathology Image. AIME 2020: 260-269 - [c43]Jing Ke, Yiqing Shen, Jason D. Wright, Naifeng Jing, Xiaoyao Liang, Dinggang Shen:
Identifying patch-level MSI from histological images of Colorectal Cancer by a Knowledge Distillation Model. BIBM 2020: 1043-1046 - [c42]Zhuoran Song, Jianfei Wang, Tianjian Li, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing:
GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor Cores. DAC 2020: 1-6 - [c41]Tao Yang, Yunkun Liao, Jianping Shi, Yun Liang, Naifeng Jing, Li Jiang:
A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern. FPL 2020: 254-261 - [c40]Zihan Zhang, Taozhong Li, Ning Guan, Qin Wang, Guanghui He, Weiguang Sheng, Zhigang Mao, Naifeng Jing:
Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration. ACM Great Lakes Symposium on VLSI 2020: 345-350 - [c39]Zhaoming Jiang, Zhuoran Song, Xiaoyao Liang, Naifeng Jing:
PRArch: Pattern-Based Reconfigurable Architecture for Deep Neural Network Acceleration. HPCC/DSS/SmartCity 2020: 122-129 - [c38]Zhuoran Song, Bangqi Fu, Feiyang Wu, Zhaoming Jiang, Li Jiang, Naifeng Jing, Xiaoyao Liang:
DRQ: Dynamic Region-based Quantization for Deep Neural Network Acceleration. ISCA 2020: 1010-1021 - [c37]Tu Hong, Ning Guan, Chen Yin, Qin Wang, Jianfei Jiang, Jing Jin, Guanghui He, Naifeng Jing:
Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array. ISCAS 2020: 1-5 - [c36]Ran Wang, Yuekang Guo, Jing Jin, Xiaoming Liu, Naifeng Jing, Jianjun Zhou:
A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers. ISCAS 2020: 1-4 - [c35]Zhuoran Song, Feiyang Wu, Xueyuan Liu, Jing Ke, Naifeng Jing, Xiaoyao Liang:
VR-DANN: Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration. MICRO 2020: 698-710 - [c34]Tao Zhou, Yongxin Zhu, Naifeng Jing, Tianhao Nan, Wanyi Li, Bo Peng:
Reliable SoC Design and Implementation of SHA-3-HMAC Algorithm with Attack Protection. SmartCloud 2020: 88-93 - [c33]B. O. Peng, Yongxin Zhu, Naifeng Jing, Xiaoying Zheng, Yueying Zhou:
Design of a Hardware Accelerator for Zero-Knowledge Proof in Blockchains. SmartCom 2020: 136-145
2010 – 2019
- 2019
- [j16]Shuo Zhang, Guanghui He, Hai-Bao Chen, Naifeng Jing, Qin Wang:
Scale Adaptive Proposal Network for Object Detection in Remote Sensing Images. IEEE Geosci. Remote. Sens. Lett. 16(6): 864-868 (2019) - [j15]Yanan Sun, Jiawei Gu, Weifeng He, Qin Wang, Naifeng Jing, Zhigang Mao, Weikang Qian, Li Jiang:
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 753-757 (2019) - [j14]Taozhong Li, Qin Wang, Yongxin Zhu, Jianfei Jiang, Guanghui He, Jing Jin, Zhigang Mao, Naifeng Jing:
A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. ACM Trans. Design Autom. Electr. Syst. 24(2): 25:1-25:22 (2019) - [j13]Li Jiang, Zhuoran Song, Haiyue Song, Chengwen Xu, Qiang Xu, Naifeng Jing, Weifeng Zhang, Xiaoyao Liang:
Energy-Efficient and Quality-Assured Approximate Computing Framework Using a Co-Training Method. ACM Trans. Design Autom. Electr. Syst. 24(6): 59:1-59:25 (2019) - [j12]Qin Wang, Zechen Liu, Jianfei Jiang, Naifeng Jing, Weiguang Sheng:
A New Cellular-Based Redundant TSV Structure for Clustered Faults. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 458-467 (2019) - [c32]Houxiang Ji, Li Jiang, Tianjian Li, Naifeng Jing, Jing Ke, Xiaoyao Liang:
HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing. ASP-DAC 2019: 249-254 - [c31]Jianfei Wang, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing:
A sharing-aware L1.5D cache for data reuse in GPGPUs. ASP-DAC 2019: 388-393 - [c30]Sijie Zheng, Hongjun You, Guanghui He, Qin Wang, Tao Si, Jianfei Jiang, Jing Jin, Naifeng Jing:
A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. ISCAS 2019: 1-5 - 2018
- [j11]Li Jiang, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, Xiaoyao Liang:
CNFET-Based High Throughput SIMD Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1331-1344 (2018) - [j10]Jianfei Wang, Qin Wang, Li Jiang, Chao Li, Xiaoyao Liang, Naifeng Jing:
IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs. IEEE Trans. Parallel Distributed Syst. 29(3): 586-599 (2018) - [c29]Haiyue Song, Xiang Song, Tianjian Li, Hao Dong, Naifeng Jing, Xiaoyao Liang, Li Jiang:
A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only). FPGA 2018: 286 - [c28]Zhenghao Peng, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, Li Jiang:
AXNet: approximate computing using an end-to-end trainable neural network. ICCAD 2018: 11:1-11:8 - [c27]Haiyue Song, Chengwen Xu, Qiang Xu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang, Li Jiang:
Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators. ICCAD 2018: 50 - [i2]Zhenghao Peng, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, Li Jiang:
AXNet: ApproXimate computing using an end-to-end trainable neural network. CoRR abs/1807.10458 (2018) - [i1]Haiyue Song, Chengwen Xu, Qiang Xu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang, Li Jiang:
Invocation-driven Neural Approximate Computing with a Multiclass-Classifier and Multiple Approximators. CoRR abs/1810.08379 (2018) - 2017
- [j9]Jianfei Wang, Fengfeng Fan, Li Jiang, Xiaoyao Liang, Naifeng Jing:
Incorporating selective victim cache into GPGPU for high-performance computing. Concurr. Comput. Pract. Exp. 29(24) (2017) - [j8]Wei Jin, Weifeng He, Jianfei Jiang, Haichao Huang, Xuejun Zhao, Yanan Sun, Xin Chen, Naifeng Jing:
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS. Integr. 58: 27-34 (2017) - [j7]Naifeng Jing, Shunning Jiang, Shuang Chen, Jingjie Zhang, Li Jiang, Chao Li, Xiaoyao Liang:
Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 520-533 (2017) - [c26]Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, Li Jiang:
Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique. DAC 2017: 38:1-38:6 - [c25]Chengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao Liang, Li Jiang:
On Quality Trade-off Control for Approximate Computing Using Iterative Training. DAC 2017: 52:1-52:6 - [c24]Xinchi Gao, Licheng Xu, Jing Jin, Naifeng Jing, Jianjun Zhou:
A wideband simplified transformer-based VCO with digital amplitude calibration. MWSCAS 2017: 787-790 - 2016
- [j6]Naifeng Jing, Li Jiang, Tao Zhang, Chao Li, Fengfeng Fan, Xiaoyao Liang:
Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs. IEEE Trans. Computers 65(1): 122-135 (2016) - [j5]Tianjian Li, Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang:
A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1192-1205 (2016) - [c23]Naifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He, Zhigang Mao:
Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. FPT 2016: 233-236 - [c22]Tianjian Li, Li Jiang, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang:
CNFET-based high throughput register file architecture. ICCD 2016: 662-669 - [c21]Fengfeng Fan, Jianfei Wang, Li Jiang, Xiaoyao Liang, Naifeng Jing:
Applying Victim Cache in High Performance GPGPU Computing. ISPDC 2016: 24-29 - [c20]Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li, Xiaoyao Liang:
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs. MICRO 2016: 14:1-14:12 - 2015
- [j4]Tao Zhang, Naifeng Jing, Kaiming Jiang, Wei Shu, Min-You Wu, Xiaoyao Liang:
Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs. ACM Trans. Archit. Code Optim. 12(2): 16:1-16:23 (2015) - [c19]Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang:
Jump test for metallic CNTs in CNFET-based SRAM. DAC 2015: 16:1-16:6 - [c18]Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao:
Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. ICCAD 2015: 764-769 - [c17]Naifeng Jing, Shuang Chen, Shunning Jiang, Li Jiang, Chao Li, Xiaoyao Liang:
Bank stealing for conflict mitigation in GPGPU Register File. ISLPED 2015: 55-60 - [c16]Xiangyu Wu, Yuanfang Xia, Naifeng Jing, Xiaoyao Liang:
CGSharing: Efficient content sharing in GPU-based cloud gaming. ISLPED 2015: 171-176 - [c15]Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim, Xiaoyao Liang, Qiang Xu:
On diagnosable and tunable 3D clock network design for lifetime reliability enhancement. ITC 2015: 1-10 - [c14]Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao:
Resource-saving compile flow for coarse-grained reconfigurable architectures. ReConFig 2015: 1-8 - [c13]Chen Wang, Li Jiang, Shiyan Hu, Tianjian Li, Xiaoyao Liang, Naifeng Jing, Weikang Qian:
Timing-driven placement for carbon nanotube circuits. SoCC 2015: 362-367 - 2014
- [j3]Zhe Feng, Naifeng Jing, Lei He:
IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2225-2228 (2014) - 2013
- [c12]Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang:
An energy-efficient and scalable eDRAM-based register file architecture for GPGPU. ISCA 2013: 344-355 - [c11]Naifeng Jing, Haopeng Liu, Yao Lu, Xiaoyao Liang:
Compiler assisted dynamic register file in GPGPU. ISLPED 2013: 3-8 - 2012
- [j2]Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He:
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. ACM Trans. Design Autom. Electr. Syst. 18(1): 13:1-13:18 (2012) - [c10]Ju-Yueh Lee, Cheng-Ru Chang, Naifeng Jing, Juexiao Su, Shi-Jie Wen, Rick Wong, Lei He:
Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs. FPT 2012: 23-28 - [c9]Bingjing Ge, Naifeng Jing, Weifeng He, Zhigang Mao:
Contention and energy aware mapping for real-time applications on Network-on-Chip. ISOCC 2012: 72-76 - 2011
- [c8]Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He:
Fault modeling and characteristics of SRAM-based FPGAs (abstract only). FPGA 2011: 279 - [c7]Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He:
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. FPL 2011: 282-285 - [c6]Zhe Feng, Naifeng Jing, GengSheng Chen, Yu Hu, Lei He:
IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs. FPL 2011: 482-485 - [c5]Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He:
Mitigating FPGA interconnect soft errors by in-place LUT inversion. ICCAD 2011: 582-586 - [c4]Li Xie, Weifeng He, Naifeng Jing, Zhigang Mao:
A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor. ISCAS 2011: 1952-1955 - [c3]Naifeng Jing, Weifeng He, Zhigang Mao:
A general statistical estimation for application mapping in Network-on-Chip. VLSI-SoC 2011: 172-175 - 2010
- [j1]Naifeng Jing, Weifeng He, Yongxin Zhu, Zhigang Mao:
Statistical estimation and evaluation for communication mapping in Network-on-Chip. Integr. 43(2): 220-229 (2010) - [c2]Naifeng Jing, Weifeng He, Zhigang Mao:
Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array. SoCC 2010: 260-265
2000 – 2009
- 2009
- [c1]Naifeng Jing, Zhigang Mao, Yongxin Zhu:
Statistical Estimation for Total Communication Load in Application-Specific Network-on-Chip. ICESS 2009: 109-114
Coauthor Index
[c75] [c73] [c71] [j28] [j27] [j26] [c68] [c63] [c62] [c59] [c56] [c55] [c54] [c53] [c52] [i6] [i5] [i4] [j20] [c48] [c46] [i3] [c45] [c44] [c43] [c42] [c39] [c38] [c35] [j13] [c32] [c31] [j11] [j10] [c29] [c28] [c27] [i2] [i1] [j9] [j7] [c26] [c25] [j6] [j5] [c22] [c21] [c20] [j4] [c19] [c17] [c16] [c15] [c13] [c12] [c11]
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