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Chi-Chao Wang
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2010 – 2019
- 2012
- [j4]Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao:
Leakage reduction through optimization of regular layout parameters. Microelectron. J. 43(1): 25-33 (2012) - [j3]Chi-Chao Wang, Yun Ye, Yu Cao
:
The potential of Fe-FET for robust design under variations: A compact modeling study. Microelectron. J. 43(11): 898-903 (2012) - 2010
- [j2]Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Chi-Chao Wang, Frank Liu, Sani R. Nassif, Yu Cao
:
Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 666-670 (2010) - [c5]Yun Ye, Chi-Chao Wang, Yu Cao
:
Simulation of random telegraph Noise with 2-stage equivalent circuit. ICCAD 2010: 709-713 - [c4]Jungseob Lee, Chi-Chao Wang, Hamid Reza Ghasemi, Lloyd Bircher, Yu Cao
, Nam Sung Kim:
Workload-adaptive process tuning strategy for power-efficient multi-core processors. ISLPED 2010: 225-230
2000 – 2009
- 2009
- [j1]Yu Cao
, Asha Balijepalli, Saurabh Sinha, Chi-Chao Wang, Wenping Wang, Wei Zhao:
The Predictive Technology Model in the Late Silicon Era and Beyond. Found. Trends Electron. Des. Autom. 3(4): 305-401 (2009) - [c3]Xia Li, Wei Zhao, Yu Cao
, Zhi Zhu, Jooyoung Song, David Bang, Chi-Chao Wang, Seung-Hyuk Kang, Joseph Wang, Matt Nowak, Nick Yu:
Pathfinding for 22nm CMOS designs using Predictive Technology Models. CICC 2009: 227-230 - [c2]Chi-Chao Wang, Wei Zhao, Frank Liu, Min Chen, Yu Cao:
Modeling of layout-dependent stress effect in CMOS design. ICCAD 2009: 513-520 - 2008
- [c1]Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao:
Design rule optimization of regular layout for leakage reduction in nanoscale design. ASP-DAC 2008: 474-479
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