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2020 – today
- 2024
[j24]Anindan Mondal
, Archisman Ghosh, Shubrojyoti Karmakar, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen:
Identification of Hardware Trojan in Gate-Level Netlist. J. Circuits Syst. Comput. 33(9) (2024)- 2023
- [j23]Abhishek Kesarwani, Sunanda Das, Mamata Dalui, Dakshina Ranjan Kisku, Bibhash Sen, Suchismita Roy, Anupam Basu:
Non-invasive anaemia detection by examining palm pallor: A smartphone-based approach. Biomed. Signal Process. Control. 79(Part): 104045 (2023) - [j22]Sunanda Das, Abhishek Kesarwani, Mamata Dalui, Dakshina Ranjan Kisku, Bibhash Sen, Suchismita Roy, Anupam Basu:
Smartphone-based non-invasive haemoglobin level estimation by analyzing nail pallor. Biomed. Signal Process. Control. 85: 104959 (2023) - [j21]Anindan Mondal, Debasish Kalita, Archisman Ghosh, Suchismita Roy, Bibhash Sen:
Toward the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity. ACM J. Emerg. Technol. Comput. Syst. 19(4): 29:1-29:16 (2023) - [j20]Anindan Mondal, Shubrojyoti Karmakar, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen, Anupam Chattopadhyay:
Hardware Trojan Detection using Transition Probability with Minimal Test Vectors. ACM Trans. Embed. Comput. Syst. 22(1): 11:1-11:21 (2023) - 2022
- [j19]Suchandra Banerjee, Suchismita Roy:
Power aware floorplanning in multiple supply voltage domain. Int. J. Circuit Theory Appl. 50(2): 382-393 (2022) - [j18]Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee:
Congestion-Aware Rectilinear Steiner Tree Construction Using PB-SAT. J. Circuits Syst. Comput. 31(9): 2250165:1-2250165:25 (2022) - 2021
- [j17]Anindan Mondal, Rajesh Kumar Biswal, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen:
Hardware Trojan Free Netlist Identification: A Clustering Approach. J. Electron. Test. 37(3): 317-328 (2021) - [j16]Suchandra Banerjee, Suchismita Roy:
Thermal-Driven Floorplanning for Fixed Outline Layouts. J. Circuits Syst. Comput. 30(5): 2150079:1-2150079:19 (2021) - [c13]Sourav Roy, Dipnarayan Das, Anindan Mondal, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen:
PUF based Lightweight Authentication and Key Exchange Protocol for IoT. SECRYPT 2021: 698-703 - 2020
- [j15]Sanjib Sadhu, Sasanka Roy, Soumen Nandi, Subhas C. Nandy, Suchismita Roy:
Efficient Algorithm for Computing the Triangle Maximizing the Length of Its Smallest Side Inside a Convex Polygon. Int. J. Found. Comput. Sci. 31(4): 421-443 (2020) - [j14]Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee:
Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based Methodology. J. Circuits Syst. Comput. 29(4): 2050057:1-2050057:22 (2020) - [j13]Sanjib Sadhu, Xiaozhou He, Sasanka Roy, Subhas C. Nandy, Suchismita Roy:
Corrigendum to: "Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares" [Theor. Comput. Sci. 769 (2019) 63-74]. Theor. Comput. Sci. 806: 632-640 (2020)
2010 – 2019
- 2019
- [j12]Shukla Banik, Suchismita Roy, Bibhash Sen:
An Integrated Framework for Application Independent Testing of FPGA Interconnect. J. Electron. Test. 35(5): 729-740 (2019) - [j11]Khushbu Chandrakar, Suchismita Roy:
A SAT-Based Methodology for Effective Clock Gating for Power Minimization. J. Circuits Syst. Comput. 28(1): 1950011:1-1950011:17 (2019) - [j10]Sanjib Sadhu, Sasanka Roy, Subhas C. Nandy, Suchismita Roy:
Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares. Theor. Comput. Sci. 769: 63-74 (2019) - [j9]Shukla Banik, Suchismita Roy, Bibhash Sen:
Application-Dependent Testing of FPGA Interconnect Network. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2296-2304 (2019) - [c12]Anindan Mondal, Mahabub Hasan Mahalat, Suraj Mandal, Suchismita Roy, Bibhash Sen:
A Novel Test Vector Generation Method for Hardware Trojan Detection. SoCC 2019: 80-85 - [c11]Shukla Banik, Suchismita Roy, Bibhash Sen:
Test Configuration Generation for Different FPGA Architectures for Application Independent Testing. VLSID 2019: 395-400 - [i3]Sanjib Sadhu, Xiaozhou He, Sasanka Roy, Subhas C. Nandy, Suchismita Roy:
Corrigendum to: "Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares", Theoretical Computer Science 769 (2019) 63-74. CoRR abs/1909.09445 (2019) - 2018
- [j8]Khushbu Chandrakar, Sudeshna Kundu, Suchismita Roy:
Power Optimization Techniques for High-Level Designs Using Multiple Voltage Components for Low Power Consumption. J. Low Power Electron. 14(2): 275-284 (2018) - [c10]Anindan Mondal, Mahabub Hasan Mahalat, Anudeep Reddy Medapati, Suchismita Roy, Bibhash Sen:
XOR based Methodology to Detect Hardware Trojan utilizing the Transition Probability. ISED 2018: 215-219 - 2017
- [j7]Shyamapada Mukherjee, Suchismita Roy:
Via-Aware Dogleg Routing Using Boolean Satisfiability. J. Circuits Syst. Comput. 26(4): 1750064:1-1750064:24 (2017) - [c9]Sanjib Sadhu, Sasanka Roy, Subhas C. Nandy, Suchismita Roy:
Optimal Covering and Hitting of Line Segments by Two Axis-Parallel Squares. COCOON 2017: 457-468 - [c8]Sanjib Sadhu, Sasanka Roy, Soumen Nandi, Subhas C. Nandy, Suchismita Roy:
Computing the Triangle Maximizing the Length of Its Smallest Side Inside a Convex Polygon. ICCSA (2) 2017: 509-524 - [c7]Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee:
K-nearest neighbour (KNN) approach using SAT based technique for rectilinear steiner tree construction. ISED 2017: 1-5 - [i2]Sanjib Sadhu, Sasanka Roy, Subhas C. Nandy, Suchismita Roy:
A linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares. CoRR abs/1709.04870 (2017) - [i1]Suchandra Banerjee, Anand Ratna, Suchismita Roy:
Satisfiability Modulo Theory based Methodology for Floorplanning in VLSI Circuits. CoRR abs/1709.07241 (2017) - 2016
- [j6]Shyamapada Mukherjee, Suchismita Roy:
Nearly-2-SAT Solutions for Segmented-Channel Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 128-140 (2016) - [c6]Suchandra Banerjee, Anand Ratna, Suchismita Roy:
Satisfiability modulo theory based methodology for floorplanning in VLSI circuits. ISED 2016: 91-95 - 2015
- [j5]Shyamapada Mukherjee, Suchismita Roy:
SAT based solutions for detailed routing of island style FPGA architectures. Microelectron. J. 46(8): 706-715 (2015) - [c5]Shyamapada Mukherjee, Suchismita Roy:
Multi terminal net routing for island style FPGAs using nearly-2-SAT computation. VDAT 2015: 1-6 - 2013
- [c4]Khushbu Chandrakar, Suchismita Roy:
SAT based low power binding to reduce switching activity. IC3 2013: 175-180 - [c3]Shyamapada Mukherjee, Jibesh Patra, Suchismita Roy:
Congestion Balancing Global Router. VDAT 2013: 223-232 - 2012
- [j4]Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta:
SAT based timing analysis for fixed and rise/fall gate delay models. Integr. 45(4): 357-364 (2012) - 2010
- [j3]Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta:
Bounded delay timing analysis and power estimation using SAT. Microelectron. J. 41(5): 317-324 (2010)
2000 – 2009
- 2008
- [j2]Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta:
Satisfiability Models for Maximum Transition Power. IEEE Trans. Very Large Scale Integr. Syst. 16(8): 941-951 (2008) - 2007
- [j1]Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta:
Event propagation for accurate circuit delay calculation using SAT. ACM Trans. Design Autom. Electr. Syst. 12(3): 36:1-36:23 (2007) - [c2]Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta:
Bounded Delay Timing Analysis Using Boolean Satisfiability. VLSI Design 2007: 295-302 - 2005
- [c1]Suchismita Roy, Sayantan Das, Prasenjit Basu, Pallab Dasgupta, Partha Pratim Chakrabarti:
SAT based solutions for consistency problems in formal property specifications for open systems. ICCAD 2005: 885-888
Coauthor Index
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