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Aditya Japa
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2020 – today
- 2024
- [c9]Venu Birudu, Tirumalarao Kadiyam, Koteswararao Penumalli, Aditya Japa, Sushma Nirmala Sambatur, Chongyan Gu, Siva Sankar Yellampalli, Ramesh Vaddi:
Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices. ISCAS 2024: 1-5 - [c8]Aditya Japa, Jack Miskelly, Yijun Cui, Máire O'Neill, Chongyan Gu:
A Novel Methodology for Processor based PUF in Approximate Computing. ISCAS 2024: 1-5 - 2023
- [j7]Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi:
Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design. Microelectron. J. 133: 105711 (2023) - [c7]Aditya Japa, Jiliang Zhang, Weiqiang Liu, Chongyan Gu:
Processor based Intrinsic PUF Design for Approximate Computing: Faith or Reality? AsianHOST 2023: 1-6 - 2022
- [j6]Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi:
Negative capacitance FETs for energy efficient and hardware secure logic designs. Microelectron. J. 119: 105320 (2022) - [c6]Kunal Kranti Das, Aditya Japa, Deepika Gupta:
A Reconfigurable Arbiter PUF Based on VGSOT MTJ. VDAT 2022: 320-330 - 2021
- [j5]Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi:
Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things. Int. J. Circuit Theory Appl. 49(8): 2299-2311 (2021) - [c5]Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi:
Steep Switching NCFET based Logic for Future Energy Efficient Electronics. iSES 2021: 327-330 - 2020
- [j4]Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi:
Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator. IET Circuits Devices Syst. 14(5): 640-647 (2020) - [j3]Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi:
Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage. Int. J. Circuit Theory Appl. 48(4): 524-538 (2020) - [c4]Aditya Japa, Palagani Yellappa, Venkateswarlu Gonuguntla, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Jun Rim Choi, Ramesh Vaddi:
A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j2]Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi:
Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks. IET Circuits Devices Syst. 13(5): 689-695 (2019) - 2018
- [c3]Aditya Japa, T. Nagateja, Santosh Kumar Vishvakarma, Palagani Yellappa, Jun Rim Choi, Ramesh Vaddi:
Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities. ISCAS 2018: 1-5 - 2017
- [c2]Aditya Japa, T. Nagateja, Ramesh Vaddi:
Tunneling Field Effect Transistors for Energy Efficient Logic, Sensor Interface and 3D IC Circuits for IoT Platforms. iNIS 2017: 90-92 - [c1]Aditya Japa, Harshita Vallabhaneni, Ramesh Vaddi:
Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs. VDAT 2017: 259-269 - 2016
- [j1]Aditya Japa, Harshita Vallabhaneni, Ramesh Vaddi:
Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction. IET Circuits Devices Syst. 10(6): 522-527 (2016)
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last updated on 2024-07-17 20:29 CEST by the dblp team
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