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2010 – 2019
- 2014
[j4]Qing Shang, Yibo Fan, Weiwei Shen, Sha Shen, Xiaoyang Zeng:
Single-Port SRAM-Based Transpose Memory With Diagonal Data Mapping for Large Size 2-D DCT/IDCT. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2422-2426 (2014)- 2013
- [j3]Sha Shen, Weiwei Shen, Yibo Fan, Xiaoyang Zeng:
A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC. IEICE Electron. Express 10(11): 20130272 (2013) - [j2]Sha Shen, Weiwei Shen, Yibo Fan, Xiaoyang Zeng:
A Unified Forward/Inverse Transform Architecture for Multi-Standard Video Codec Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(7): 1534-1542 (2013) - [c5]Weiwei Shen, Qing Shang, Sha Shen, Yibo Fan, Xiaoyang Zeng:
A high-throughput VLSI architecture for deblocking filter in HEVC. ISCAS 2013: 673-676 - 2012
- [c4]Sha Shen, Weiwei Shen, Yibo Fan, Xiaoyang Zeng:
A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards. ICME 2012: 788-793 - [c3]Huibo Zhong, Sha Shen, Yibo Fan, Xiaoyang Zeng:
A Low Complexity Macroblock Layer Rate Control Scheme Base on Weighted-Window for H.264 Encoder. MMM 2012: 563-573 - 2011
- [j1]Huibo Zhong, Sha Shen, Yibo Fan, Xiaoyang Zeng:
A 4-way parallel CAVLC design for H.264/AVC 4Kx2K 60fps encoder. IEICE Electron. Express 8(22): 1863-1869 (2011) - [c2]Sha Shen, Huibo Zhong, Yibo Fan, Xiaoyang Zeng:
A hardware/software co-design approach for multiple-standard video bitstream parsing. ASICON 2011: 43-46 - [c1]Huibo Zhong, Sha Shen, Yibo Fan, Xiaoyang Zeng:
A two-way parallel CAVLC encoder for 4K×2K H.264/AVC. ASICON 2011: 75-78
Coauthor Index
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