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2020 – today
- 2024
[c9]Dai Cheol Jung, Max Ruttenberg, Paul Gao, Scott Davidson, Daniel Petrisko, Kangli Li, Aditya K. Kamath, Lin Cheng, Shaolin Xie, Peitian Pan, Zhongyuan Zhao, Zichao Yue, Bandhav Veluri, Sripathi Muralitharan, Adrian Sampson, Andrew Lumsdaine, Zhiru Zhang, Christopher Batten, Mark Oskin, Dustin Richmond, Michael Bedford Taylor:
Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore. ISCA 2024: 770-784- 2020
- [j3]Dong-Hyeon Park
, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Bedford Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski:
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. IEEE J. Solid State Circuits 55(4): 933-944 (2020)
2010 – 2019
- 2019
- [c8]Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski:
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. VLSI Circuits 2019: 30- - [c7]Subhankar Pal, Dong-Hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael B. Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski:
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. VLSI Circuits 2019: 150- - 2018
- [j2]Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, Michael B. Taylor:
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. IEEE Micro 38(2): 30-41 (2018) - [j1]Shaolin Xie, Scott Davidson, Ikuo Magaki, Moein Khazraee, Luis Vega, Lu Zhang, Michael B. Taylor:
Extreme Datacenter Specialization for Planet-Scale Computing: ASIC Clouds. ACM SIGOPS Oper. Syst. Rev. 52(1): 96-108 (2018) - [c6]Peng Guo, Hong Ma, Ruizhi Chen, Pin Li, Shaolin Xie, Donglin Wang:
FBNA: A Fully Binarized Neural Network Accelerator. FPL 2018: 51-54 - [c5]Ruizhi Chen, Hong Ma, Peng Guo, Shaolin Xie, Pin Li, Donglin Wang:
Low Latency Spiking ConvNets with Restricted Output Training and False Spike Inhibition. IJCNN 2018: 1-8 - [c4]Ruizhi Chen, Hong Ma, Shaolin Xie, Peng Guo, Pin Li, Donglin Wang:
Fast and Efficient Deep Sparse Multi-Strength Spiking Neural Networks with Dynamic Pruning. IJCNN 2018: 1-8 - [c3]Yang Guo, Shaolin Xie, Zijun Liu, Lei Yang, Donglin Wang:
Parallel Polar Encoding in 5G Communication. ISCC 2018: 64-69 - [i1]Shaolin Xie, Michael B. Taylor:
The BaseJump Manycore Accelerator Network. CoRR abs/1808.00650 (2018) - 2017
- [c2]Lei Yang, Shaolin Xie, Zijun Liu, Xueliang Du, Donglin Wang:
A self-indexed register file for efficient arithmetical computing hardware. CEEC 2017: 13-18 - 2016
- [c1]Donglin Wang, Xueliang Du, Leizu Yin, Chen Lin, Hong Ma, Weili Ren, Huijuan Wang, Xingang Wang, Shaolin Xie, Lei Wang, Zijun Liu, Tao Wang, Zhonghua Pu, Guangxin Ding, Mengchen Zhu, Lipeng Yang, Ruoshan Guo, Zhiwei Zhang, Xiao Lin, Jie Hao, Yongyong Yang, Wenqin Sun, Fabiao Zhou, NuoZhou Xiao, Qian Cui, Xiaoqin Wang:
MaPU: A novel mathematical computing architecture. HPCA 2016: 457-468
Coauthor Index
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