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2010 – 2019
- 2017
[j4]Fazil Ahmad
, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori:
A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling. IEEE J. Solid State Circuits 52(1): 21-32 (2017)- 2016
- [c2]Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori:
19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC. ISSCC 2016: 324-325 - 2015
- [j3]Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori:
A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS. IEEE J. Solid State Circuits 50(4): 856-866 (2015) - 2014
- [c1]Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori:
A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS. VLSIC 2014: 1-2
2000 – 2009
- 2008
- [j2]Ali Afsahi, Jacob J. Rael, Arya Behzad, Hung-Ming Chien, Michael Pan, Stephen Au, Adedayo Ojo, C. Paul Lee, Seema Butala Anand, Kevin Chien, Stephen Wu, Rozi Roufoogaran, Alireza Zolfaghari, John C. Leete, Long H. Tran, Keith A. Carter, Mohammad Nariman, David W. K. Yeung, Walter Morton, Mark Gonikberg, Mukul Seth, Marcellus Forbes, Jay Pattin, Luis Gutierrez, Sumant Ranganathan, Ning Li, Eric Blecker, Jack Lin, Tom Kwan, Rose Zhu, Mark Chambers, Maryam Rofougaran, Ahmadreza Rofougaran, Jason Trachewsky, Pieter van Rooyen:
A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit. IEEE J. Solid State Circuits 43(5): 1101-1118 (2008)
1990 – 1999
- 1996
- [j1]Kavch Parsi, Robert P. Burns, Alan Chaiken, Mark Chambers, William R. Forni, David Harnishfeger, Scott Kaylor, Micheal J. Pennell, Jose O. Perez, Narendra Rao, Mark Rohrhaugh, Mike Ross, Gary L. Stuhlmiller:
A PRML read/write channel IC using analog signal processing for 200 Mb/s HDD. IEEE J. Solid State Circuits 31(11): 1817-1830 (1996)
Coauthor Index
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