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ORCIDSk. Noor Mahammad
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2020 – today
- 2024
[j31]L. Hemanth Krishna
, Ayesha Sk, J. Bhaskara Rao, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor. IEEE Embed. Syst. Lett. 16(2): 134-137 (2024)- [j30]Dhayalakumar M, Sk. Noor Mahammad:
TeRa: Ternary and Range based packet classification engine. Integr. 96: 102153 (2024) - [j29]S. Deepanjali, S. K. Noor Mahammad:
A twofold bio-inspired system for mitigating SEUs in the controllers of digital system deployed on FPGA. J. Supercomput. 80(7): 9438-9470 (2024) - [j28]S. Deepanjali, Sk. Noor Mahammad:
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware. ACM Trans. Design Autom. Electr. Syst. 29(2): 31:1-31:29 (2024) - [c19]Raghavendra Kumar Sakali, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Fault-Tolerant Floating-Point Multiplier Design for Mission Critical Systems. VLSID 2024: 678-683 - 2023
- [j27]Raghavendra Kumar Sakali, Sk. Noor Mahammad:
Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction Algorithm. J. Electron. Test. 39(1): 111-122 (2023) - [j26]S. Skandha Deepsita, T. Karthikeyan, Sk. Noor Mahammad:
Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications. Integr. 92: 24-34 (2023) - [j25]Raghavendra Kumar Sakali, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs. Integr. 93: 102068 (2023) - [j24]Raghavendra Kumar Sakali, P. Balasubramanian, Ramesh Reddy, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Optimized Fault-Tolerant Adder Design Using Error Analysis. J. Circuits Syst. Comput. 32(6): 2350091:1-2350091:32 (2023) - [j23]Dhayalakumar M, Sk. Noor Mahammad:
Deterministic Approach for Range-enhanced Reconfigurable Packet Classification Engine. ACM Trans. Reconfigurable Technol. Syst. 16(2): 29:1-29:26 (2023) - [c18]Veeramani Sonai, Indira Bharathi, Sk. Noor Mahammad:
A Perspective of IP Lookup Approach Using Graphical Processing Unit (GPU). ICDCIT 2023: 98-103 - 2022
- [j22]Chinthalgiri Jyothi, Saranya Karunamurthi, Bhaskara Rao Jammu, Sreehari Veeramachaneni, Sk. Noor Mahammad:
A New Approximate 4-2 Compressor using Merged Sum and Carry. J. Electron. Test. 38(4): 381-394 (2022) - [j21]S. Deepanjali, Sk. Noor Mahammad:
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach. J. Electron. Test. 38(5): 547-565 (2022) - [j20]S. Skandha Deepsita, Sk. Noor Mahammad:
Low power, high speed approximate multiplier for error resilient applications. Integr. 84: 37-46 (2022) - [j19]S. M. Srinivasavarma Vegesna, Shanmukha Rao Pydi, Sk. Noor Mahammad:
Hardware-based multi-match packet classification in NIDS: an overview and novel extensions for improving the energy efficiency of TCAM-based classifiers. J. Supercomput. 78(11): 13086-13121 (2022) - [j18]S. Skandha Deepsita, Dhayala Kumar M, Sk. Noor Mahammad:
Energy Efficient Error Resilient Multiplier Using Low-power Compressors. ACM Trans. Design Autom. Electr. Syst. 27(3): 21:1-21:26 (2022) - [c17]B. S. Chandrasekhar, S. Deepanjali, Sk. Noor Mahammad:
Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA. iSES 2022: 31-35 - [c16]Sandeep Kolla, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Logic Locking Designs at Transistor Level for Full Adders. iSES 2022: 289-292 - 2021
- [j17]Y. Mounica, K. Naresh Kumar, Sreehari Veeramachaneni, S. K. Noor Mahammad:
Energy efficient signed and unsigned radix 16 booth multiplier design. Comput. Electr. Eng. 90: 106892 (2021) - [j16]L. Hemanth Krishna, Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, S. K. Noor Mahammad:
Efficient design of 15: 4 counter using a novel 5: 3 counter for high-speed multiplication. IET Comput. Digit. Tech. 15(1): 12-19 (2021) - [j15]S. M. Srinivasavarma Vegesna, Shiv Vidhyut, Sk. Noor Mahammad:
A TCAM-based Caching Architecture Framework for Packet Classification. ACM Trans. Embed. Comput. Syst. 20(1): 2:1-2:19 (2021) - [c15]L. Hemanth Krishna, J. Bhaskara Rao, Ayesha Sk, Sreehari Veeramachaneni, S. K. Noor Mahammad:
Energy Efficient Approximate 4: 2 Compressors for Error Tolerant Applications. ICECS 2021: 1-6 - [c14]Sandeep Kolla, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Design and Analysis of Obfuscated Full Adders. ICM 2021: 49-52 - [c13]L. Hemanth Krishna, J. Bhaskara Rao, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Energy Efficient Approximate Multiplier Design for Image/Video Processing Applications. iSES 2021: 210-215 - [c12]S. Skandha Deepsita, Kuchipudi Divya, Sk. Noor Mahammad:
Energy Efficient and Multiplierless Approximate Integer DCT Implementation for HEVC. VLSI-SoC 2021: 1-6 - 2020
- [j14]Chandana Mounica, Sagar Krishna, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Efficient implementation of mixed-precision multiply-accumulator unit for AI algorithms. Int. J. Circuit Theory Appl. 48(8): 1386-1394 (2020) - [j13]S. Veeramani, Sk. Noor Mahammad:
An Approach to Place Sink Node in a Wireless Sensor Network (WSN). Wirel. Pers. Commun. 111(2): 1117-1127 (2020)
2010 – 2019
- 2019
- [j12]S. M. Srinivasavarma Vegesna, Ashok Chakravarthy Nara, Sk. Noor Mahammad:
A Novel Rule Mapping on TCAM for Power Efficient Packet Classification. ACM Trans. Design Autom. Electr. Syst. 24(5): 48:1-48:23 (2019) - [j11]M. Mohamed Asan Basiri, Sk. Noor Mahammad:
Discrete Orthogonal Multi-transform on Chip (DOMoC). J. Signal Process. Syst. 91(5): 437-457 (2019) - 2018
- [c11]M. Mohamed Asan Basiri, Sk. Noor Mahammad:
An Efficient VLSI Architecture for Convolution Based DWT Using MAC. VLSID 2018: 271-276 - 2017
- [j10]Shanmugakumar Murugesan, Sk. Noor Mahammad:
A Novel Range Matching Architecture for Packet Classification Without Rule Expansion. ACM Trans. Design Autom. Electr. Syst. 23(1): 8:1-8:15 (2017) - [c10]M. Mohamed Asan Basiri, Sk. Noor Mahammad:
High Performance Integer DCT Architectures for HEVC. VLSID 2017: 121-126 - 2016
- [j9]M. Mohamed Asan Basiri, Sk. Noor Mahammad:
Multi-mode parallel and folded VLSI architectures for 1D-fast Fourier transform. Integr. 55: 43-56 (2016) - [j8]M. Mohamed Asan Basiri, Sk. Noor Mahammad:
An efficient VLSI architecture for lifting based 1D/2D discrete wavelet transform. Microprocess. Microsystems 47: 404-418 (2016) - [j7]M. Mohamed Asan Basiri, Sk. Noor Mahammad:
High speed multiplexer design using tree based decomposition algorithm. Microelectron. J. 51: 99-111 (2016) - [c9]M. Mohamed Asan Basiri, S. K. Noor Mahammad:
An Efficient VLSI Architecture for Discrete Hadamard Transform. VLSID 2016: 140-145 - 2015
- [j6]Rajesh Eswarawaka, S. K. Noor Mahammad, B. Eswara Reddy:
Genetic annealing with efficient strategies to improve the performance for the NP-hard and routing problems. J. Exp. Theor. Artif. Intell. 27(6): 779-788 (2015) - [j5]M. Mohamed Asan Basiri, Sk. Noor Mahammad:
Configurable Folded IIR Filter Design. IEEE Trans. Circuits Syst. II Express Briefs 62-II(12): 1144-1148 (2015) - [c8]S. Dinesh Kumar, S. K. Noor Mahammad:
A novel adiabatic SRAM cell implementation using split level charge recovery logic. VDAT 2015: 1-2 - [c7]S. Dinesh Kumar, Sk. Noor Mahammad:
A Novel Ternary Content-Addressable Memory (TCAM) Design Using Reversible Logic. VLSID 2015: 316-320 - 2014
- [j4]S. Veeramani, Sk. Noor Mahammad:
Efficient IP lookup using hybrid trie-based partitioning of TCAM-based open flow switches. Photonic Netw. Commun. 28(2): 135-145 (2014) - [j3]M. Mohamed Asan Basiri, Sk. Noor Mahammad:
An Efficient Hardware-Based Higher Radix Floating Point MAC Design. ACM Trans. Design Autom. Electr. Syst. 20(1): 15:1-15:25 (2014) - [c6]M. Mohamed Asan Basiri, S. K. Noor Mahammad:
Memory Based Multiplier Design in Custom and FPGA Implementation. ISI (1) 2014: 253-265 - [c5]Rajesh Eswarawaka, S. K. Noor Mahammad, B. Eswara Reddy:
Hybrid Memetic Algorithm for FPGA Placement and Routing Using Parallel Genetic Tunneling. SocProS (2) 2014: 359-371 - 2013
- [c4]S. Veeramani, Manas Kumar, Sk. Noor Mahammad:
Minimization of flow table for TCAM based openflow switches by virtual compression approach. IEEE ANTS 2013: 1-4 - [c3]S. Veeramani, Manas Kumar, Sk. Noor Mahammad:
Hybrid trie based partitioning of TCAM based openflow switches. IEEE ANTS 2013: 1-5 - [c2]S. Veeramani, Biraja Nalini Rout, Sk. Noor Mahammad:
Novel approach to secure channel using C-SCAN and microcontroller in openflow. IEEE ANTS 2013: 1-4 - [c1]S. Veeramani, S. Rahul Sharma, Sk. Noor Mahammad:
Constructing scalable hierarchical switched openflow network using adaptive replacement of flow table management. IEEE ANTS 2013: 1-3 - 2011
- [j2]Shoaib Mohammed, Sk. Noor Mahammad, V. Kamakoti:
Hardware based genetic evolution of self-adaptive arbitrary response FIR filters. Appl. Soft Comput. 11(1): 842-854 (2011) - 2010
- [j1]Sk. Noor Mahammad, Kamakoti Veezhinathan:
Constructing Online Testable Circuits Using Reversible Logic. IEEE Trans. Instrum. Meas. 59(1): 101-109 (2010)
Coauthor Index
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