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ORCIDDoug A. Edwards
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2010 – 2019
- 2015
[c19]Mahdi Jelodari Mamaghani, Jim D. Garside, Doug A. Edwards:
De-elastisation: from asynchronous dataflows to synchronous circuits. DATE 2015: 273-276- 2014
- [c18]Mahdi Jelodari Mamaghani, Jim D. Garside
, William B. Toms, Doug A. Edwards:
Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA. DSD 2014: 607-614 - [c17]Wei Song, Jim D. Garside, Doug A. Edwards:
Automatic data path extraction in large-scale register-transfer level designs. ISCAS 2014: 377-380 - 2013
- [j6]Zheng Xie, Doug A. Edwards:
Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits. VLSI Design 2013: 984376:1-984376:22 (2013) - 2012
- [c16]Wei Song, Doug A. Edwards, Jim D. Garside, William J. Bainbridge:
Area efficient asynchronous SDM routers using 2-stage Clos switches. DATE 2012: 1495-1500 - 2011
- [j5]Wei Song, Doug A. Edwards:
Asynchronous spatial division multiplexing router. Microprocess. Microsystems 35(2): 85-97 (2011) - 2010
- [j4]Sam Taylor, Doug A. Edwards, Luis A. Plana, Luis A. Tarazona:
Asynchronous Data-Driven Circuit Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1093-1106 (2010) - [c15]Wei Song, Doug A. Edwards:
An Asynchronous Routing Algorithm for Clos Networks. ACSD 2010: 67-76 - [c14]Wei Song, Doug A. Edwards:
A low latency wormhole router for asynchronous on-chip networks. ASP-DAC 2010: 437-443 - [c13]Zheng Xie, Doug A. Edwards:
Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits. DDECS 2010: 161-166 - [c12]Luis A. Tarazona, Doug A. Edwards, Andrew Bardsley, Luis A. Plana:
Description-Level Optimisation of Synthesisable Asynchronous Circuits. DSD 2010: 441-448
2000 – 2009
- 2009
- [c11]Andrew Bardsley, Luis A. Tarazona, Doug A. Edwards:
Teak: A Token-Flow Implementation for the Balsa Language. ACSD 2009: 23-31 - [c10]William B. Toms, Doug A. Edwards:
Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks. ASYNC 2009: 139-150 - [c9]Luis A. Tarazona, Doug A. Edwards, Luis A. Plana:
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor. DSD 2009: 627-634 - [c8]Wei Song, Doug A. Edwards:
Building asynchronous routers with independent sub-channels. SoC 2009: 48-51 - [c7]P. Balasubramanian, Doug A. Edwards:
Dual-Sum Single-Carry Self-Timed Adder Designs. ISVLSI 2009: 121-126 - [c6]Wei Song, Doug A. Edwards, José Luis Núñez-Yáñez, Sohini Dasgupta:
Adaptive stochastic routing in fault-tolerant on-chip networks. NOCS 2009: 32-37 - 2008
- [j3]José L. Núñez-Yáñez, Doug A. Edwards, Antonio Marcello Coppola:
Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems. IET Comput. Digit. Tech. 2(3): 184-198 (2008) - [c5]Sam Taylor, Doug A. Edwards, Luis A. Plana:
Automatic Compilation of Data-Driven Circuits. ASYNC 2008: 3-14 - 2007
- [c4]Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A. Tarazona, Andrew Bardsley:
Performance-driven syntax-directed synthesis of asynchronous processors. CASES 2007: 43-47 - 2005
- [c3]Luis A. Plana, Sam Taylor, Doug A. Edwards:
Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance. ICCD 2005: 703-710 - [c2]Nitin Gupta, Doug A. Edwards:
Synthesis of Asynchronous Circuits Using Early Data Validity. VLSI Design 2005: 799-803 - 2002
- [j2]Doug A. Edwards, Andrew Bardsley:
Balsa: An Asynchronous Hardware Synthesis Language. Comput. J. 45(1): 12-18 (2002) - [c1]Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley, Doug A. Edwards:
A Burst-Mode Oriented Back-End for the Balsa Synthesis System. DATE 2002: 330-337 - 2000
- [j1]Andrew Bardsley, Doug A. Edwards:
Synthesising an asynchronous DMA controller with Balsa. J. Syst. Archit. 46(14): 1309-1319 (2000)
Coauthor Index
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