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2020 – today
- 2024
[j5]Feiyu Li
, Qishen Fang, Jiangchao Wu, Yang Jiang, Pui-In Mak, Rui Paulo Martins, Man-Kay Law:
A 93.4% Peak Efficiency CLOAD-Free Multi-Phase Switched-Capacitor DC-DC Converter Achieving a Fast DVS up to 222.5 mV/ns. IEEE J. Solid State Circuits 59(6): 1747-1758 (2024)- [j4]Xin Lu, Jiangchao Wu, Zhao Wang, Yifei Xiang, Liyuan Liu, Pui-In Mak, Rui Paulo Martins, Man-Kay Law:
A 0.013 mm² 3.2-ns Input Range 10-Bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 71(8): 3635-3639 (2024) - [c5]Jiangchao Wu, Ke Hu, Xuanlin Chen, Pui-In Mak, Rui Paulo Martins, Man Kay Law:
A 0.25pJ/Comparison, 27.3μV Input Noise Dynamic Comparator Exploiting Stacked Floating Preamplifier with Cross-Coupled Feedback Inverters in 180nm CMOS. CICC 2024: 1-2 - 2023
- [c4]Jiangchao Wu, Guangshu Zhao, Litao Zhang, Yu Jia, Yang Jiang, Pui-In Mak, Rui Paulo Martins, Man Kay Law:
Fully Integrated Reconfigurable Solar Energy Harvester for $100\mu\mathrm{A}$ Burst Output Current Delivery with 78.6% Peak Energy Extraction Efficiency and Minimum Startup Incident Light Power of 0.27mW/cm2. A-SSCC 2023: 1-3 - 2022
- [c3]Yu Lei, Qishen Fang, Jiangchao Wu, Man-Kay Law, Pui-In Mak, Rui Paulo Martins:
High Linearity BJT-Based Time-Domain CMOS Temperature Sensor. APCCAS 2022: 153-156 - 2021
- [j3]Jiangchao Wu, Hou-Man Leong, Yang Jiang, Man-Kay Law, Pui-In Mak, Rui Paulo Martins:
A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 29(9): 1665-1669 (2021) - 2020
- [c2]Chuanqi Wei, Jiangchao Wu, Man-Kay Law, Pui-In Mak, Rui Paulo Martins:
Low Complexity Illumination-Invariant Motion Vector Detection Based on Logarithmic Edge Detection and Edge Difference. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j2]Jiangchao Wu, Ka-Chon Lei, Hou-Man Leong, Yang Jiang, Man-Kay Law, Pui-In Mak, Rui Paulo Martins:
Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1768-1772 (2019) - 2016
- [j1]Jiangchao Wu, Man-Kay Law, Pui-In Mak, Rui Paulo Martins:
A 2-µW 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop. IEEE Trans. Circuits Syst. II Express Briefs 63-II(4): 351-355 (2016) - 2013
- [c1]Jiangchao Wu, Man-Kay Law, Pui-In Mak, Rui Paulo Martins:
A 1.83 μW, 0.78 μVrms input referred noise neural recording front end. ISCAS 2013: 405-408
Coauthor Index
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