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2020 – today
- 2024
[c6]Yusuke Shuto, Jun Okuno, Tsubasa Yonai, Ryo Ono, Peter Reinig, Maximilian Lederer, Konrad Seidel, Ruben Alcala, Thomas Mikolajick, Uwe Schroeder, Taku Umebayashi, Kentaro Akiyama:
HZO-based Nonvolatile SRAM Array with 100% Bit Recall Yield and Sufficient Retention Time at 85°C. VLSI Technology and Circuits 2024: 1-2- 2023
- [c5]Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho, Kimiyoshi Usami, Taku Umebayashi:
A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing. VLSI Technology and Circuits 2023: 1-2 - 2021
- [c4]Jun Okuno, Takafumi Kunihiro, Kenta Konishi, Hideki Maemura, Yusuke Shuto, Fumitaka Sugaya, Monica Materano, Tarek Ali, Maximilian Lederer
, Kati Kühnel, Konrad Seidel, Uwe Schroeder, Thomas Mikolajick, Masanori Tsukamoto, Taku Umebayashi:
High-Endurance and Low-Voltage operation of 1T1C FeRAM Arrays for Nonvolatile Memory Application. IMW 2021: 1-3 - [c3]Daisuke Saito, Toshiyuki Kobayashi, Hiroki Koga, Nicolo Ronchi, Kaustuv Banerjee, Yusuke Shuto, Jun Okuno, Kenta Konishi, Luca Di Piazza, Arindam Mallik, Jan Van Houdt, Masanori Tsukamoto, Kazunobu Ohkuri, Taku Umebayashi, Takayuki Ezaki:
Analog In-memory Computing in FeFET-based 1T1R Array for Edge AI Applications. VLSI Circuits 2021: 1-2
2010 – 2019
- 2017
- [c2]Tsutomu Haruta, Tsutomu Nakajima, Jun Hashizume, Taku Umebayashi, Hiroshi Takahashi, Kazuo Taniguchi, Masami Kuroda, Hiroshi Sumihiro, Koji Enoki, Takatsugu Yamasaki, Katsuya Ikezawa, Atsushi Kitahara, Masao Zen, Masafumi Oyama, Hiroki Koga, Hidenobu Tsugawa, Tomoharu Ogita, Takashi Nagano, Satoshi Takano, Tetsuo Nomoto:
4.6 A 1/2.3inch 20Mpixel 3-layer stacked CMOS Image Sensor with DRAM. ISSCC 2017: 76-77 - 2013
- [c1]Shunichi Sukegawa, Taku Umebayashi, Tsutomu Nakajima, Hiroshi Kawanobe, Ken Koseki, Isao Hirota, Tsutomu Haruta, Masanori Kasai, Koji Fukumoto, Toshifumi Wakano, Keishi Inoue, Hiroshi Takahashi, Takashi Nagano, Yoshikazu Nitta, Teruo Hirayama, Noriyuki Fukushima:
A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor. ISSCC 2013: 484-485
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