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ORCIDDevesh Dwivedi
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2020 – today
- 2023
[c8]Ravi, Lomash Chandra Acharya, Mahipal Dargupally, Neha Gupta, Neeraj Mishra, Lalit Mohan Dani, Nilotpal Sarma, Devesh Dwivedi, Sudeb Dasgupta, Anand Bulusu:
ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications. APCCAS 2023: 100-104- [c7]Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi:
A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process. VLSID 2023: 1-6 - 2021
- [j6]Karri Manikantta Reddy
, M. H. Vasantha, Nithin Y. B. Kumar, Ch. Keshava Gopal, Devesh Dwivedi:
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications. Integr. 81: 268-279 (2021) - 2020
- [j5]Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Devesh Dwivedi:
Design of Approximate Booth Squarer for Error-Tolerant Computing. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1230-1241 (2020)
2010 – 2019
- 2019
- [j4]Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Nand Kishor Yadav, Santosh Kumar Vishvakarma, Devesh Dwivedi:
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM. Circuits Syst. Signal Process. 38(4): 1482-1505 (2019) - 2018
- [c6]Karri Manikantta Reddy, M. H. Vasantha, Kumar Y. B. Nithin, Devesh Dwivedi:
Design of Approximate Dividers for Error Tolerant Applications. MWSCAS 2018: 496-499 - 2016
- [j3]C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi:
Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications. Circuits Syst. Signal Process. 35(2): 385-407 (2016) - [j2]Bhupendra Singh Reniwal, Vikas Vijayvargiya, Santosh Kumar Vishvakarma, Devesh Dwivedi:
Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance. Circuits Syst. Signal Process. 35(9): 3066-3085 (2016) - [j1]C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi:
A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations. Microelectron. J. 51: 75-88 (2016) - [c5]C. B. Kushwah, Devesh Dwivedi, N. Sathisha, Krishnan S. Rengarajan:
A robust 8T FinFET SRAM cell with improved stability for low voltage applications. VDAT 2016: 1-6 - 2015
- [c4]Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi:
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small Icell SRAM Using FinFET. ACM Great Lakes Symposium on VLSI 2015: 95-98 - [c3]Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal, V. Sharma, C. B. Khuswah, Devesh Dwivedi:
Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity. iNIS 2015: 29-34 - 2014
- [c2]C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi:
Single-ended sub-threshold finfet 7T SRAM cell without boosted supply. ICICDT 2014: 1-4 - 2012
- [c1]Devesh Dwivedi, Suman Dwivedi, Eswararao Potladhurthi:
Voltage up level shifter with improved performance and reduced power. CCECE 2012: 1-4
Coauthor Index
aka: Nithin Y. B. Kumar
aka: Nithin Kumar Y. B.
aka: Kumar Y. B. Nithin
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