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ORCIDTheodore W. Manikas
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2020 – today
- 2024
[c21]Alexander Coyle, Hui Jiang, Jennifer Dworak, Theodore W. Manikas, Kundan Nepal:
Dual Use Circuitry for Early Failure Warning and Test. ISQED 2024: 1-8- 2023
- [j10]Hui Jiang
, Fanchen Zhang, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas:
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift. J. Electron. Test. 39(2): 227-243 (2023) - [c20]Eslam Yassien, Yongjia Xu, Hui Jiang, Thach Nguyen, Jennifer Dworak, Theodore W. Manikas, Kundan Nepal:
Harvesting Wasted Clock Cycles for Efficient Online Testing. ETS 2023: 1-6 - [i1]Andrew Havard, Theodore W. Manikas, Eric C. Larson, Mitchell A. Thornton:
CNN-Assisted Steganography - Integrating Machine Learning with Established Steganographic Techniques. CoRR abs/2304.12503 (2023) - 2021
- [j9]Soha Alhelaly, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Ping Gui, Alfred L. Crouch:
3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations. IEEE Trans. Emerg. Top. Comput. 9(2): 774-786 (2021) - [c19]Aviraj Sinha, Michael A. Taylor, Nathan Srirama, Theodore W. Manikas, Eric C. Larson, Mitchell A. Thornton:
Industrial Control System Anomaly Detection Using Convolutional Neural Network Consensus. CCTA 2021: 693-700 - [c18]Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar:
Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits. ITC 2021: 319-323
2010 – 2019
- 2019
- [j8]Yi Sun, Fanchen Zhang, Hui Jiang, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar:
Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. J. Electron. Test. 35(6): 887-900 (2019) - [c17]Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Matan Segal, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar:
Test Architecture for Fine Grained Capture Power Reduction. ICECS 2019: 558-561 - 2017
- [c16]Soha Alhelaly, Jennifer Dworak, Theodore W. Manikas, Ping Gui, Kundan Nepal, Alfred L. Crouch:
Detecting a trojan die in 3D stacked integrated circuits. NATW 2017: 1-6 - [c15]Kaitlin N. Smith, Michael A. Taylor, Anna A. Carroll, Theodore W. Manikas, Mitchell A. Thornton:
Automated Markov-chain based analysis for large state spaces. SysCon 2017: 1-8 - 2016
- [c14]Fanchen Zhang, Yi Sun, Xi Shen, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, Ping Gui, R. Iris Bahar, Al Crouch, John C. Potter:
Using Existing Reconfigurable Logic in 3D Die Stacks for Test. NATW 2016: 46-52 - [c13]Philip C. Davis, Mitchell A. Thornton, Theodore W. Manikas:
Reliability block diagram extensions for non-parametric probabilistic analysis. SysCon 2016: 1-6 - 2015
- [j7]Theodore W. Manikas, Mitchell A. Thornton, David Y. Feinstein:
Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision Diagrams. J. Multiple Valued Log. Soft Comput. 24(1-4): 135-149 (2015) - [j6]Kundan Nepal, Soha Alhelaly, Jennifer Dworak, R. Iris Bahar, Theodore W. Manikas, Ping Guikundan:
Repairing a 3-D Die-Stack Using Available Programmable Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 849-861 (2015) - [c12]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas:
Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems. ISMVL 2015: 170-175 - 2014
- [j5]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas:
On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems. IEICE Trans. Inf. Syst. 97-D(9): 2234-2242 (2014) - [c11]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas:
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams. ISMVL 2014: 190-195 - [c10]Mitchell A. Thornton, Theodore W. Manikas, Stephen A. Szygenda, Shinobu Nagayama:
System Probability Distribution Modeling Using MDDs. ISMVL 2014: 196-201 - 2013
- [c9]Kundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar:
Built-in Self-Repair in a 3D die stack using programmable logic. DFTS 2013: 243-248 - [c8]Mitchell A. Thornton, Theodore W. Manikas, Phillip A. Laplante:
Embedded and real-time systems classes in traditional and distance education format. FIE 2013: 1379-1385 - [c7]Mitchell A. Thornton, Theodore W. Manikas:
Spectral Response of Ternary Logic Netlists. ISMVL 2013: 109-116 - 2012
- [j4]Theodore W. Manikas:
Integrated Circuit Channel Routing using a Pareto-Optimal Genetic Algorithm. J. Circuits Syst. Comput. 21(5) (2012) - [c6]Theodore W. Manikas, David Y. Feinstein, Mitchell A. Thornton:
Modeling Medical System Threats with Conditional Probabilities Using Multiple-Valued Logic Decision Diagrams. ISMVL 2012: 244-249 - 2011
- [c5]Theodore W. Manikas, Mitchell A. Thornton, David Y. Feinstein:
Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities. ISMVL 2011: 263-267 - 2010
- [j3]Debarshi Chatterjee, Theodore W. Manikas:
On-chip thermal optimisation by whitespace reallocation using a constrained particleswarm optimisation algorithm. IET Circuits Devices Syst. 4(3): 251-260 (2010) - [j2]Peter G. LoPresti, Theodore W. Manikas, Jeff Kohlbeck:
An Electrical Engineering Summer Academy for Middle School and High School Students. IEEE Trans. Educ. 53(1): 18-25 (2010)
2000 – 2009
- 2009
- [j1]Kamran H. Sedighi, Theodore W. Manikas, Kaveh Ashenayi, Roger L. Wainwright:
A Genetic Algorithm for Autonomous Navigation Using Variable-Monotone Paths. Int. J. Robotics Autom. 24(4) (2009) - 2008
- [c4]Theodore W. Manikas, Dale Teeters:
Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells. ISMVL 2008: 197-201 - 2006
- [c3]Daniel A. Ashlock, Theodore W. Manikas, Kaveh Ashenayi:
Evolving A Diverse Collection of Robot Path Planning Problems. IEEE Congress on Evolutionary Computation 2006: 1837-1844 - 2004
- [c2]Kamran H. Sedighi, Kaveh Ashenayi, Theodore W. Manikas, Roger L. Wainwright, Heng-Ming Tai:
Autonomous local path planning for a mobile robot using a genetic algorithm. IEEE Congress on Evolutionary Computation 2004: 1338-1345 - 2002
- [c1]Theodore W. Manikas, Gerald R. Kane:
Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement. IWLS 2002: 27-30
Coauthor Index
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