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António Canelas
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2020 – today
- 2022
- [c20]Fábio Passos, Rafael Vieira, António Canelas, Ricardo Póvoa, Nuno Lourenço, Nuno Horta, Jorge Guilherme:
A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/°C Stability for Space Applications. ISCAS 2022: 1-5 - 2021
- [j16]António Canelas, Fábio Passos, Nuno Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández:
Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs. IEEE Access 9: 124152-124164 (2021) - 2020
- [j15]Ricardo Póvoa, António Canelas, Ricardo Martins, Nuno Horta, Nuno Lourenço, João Goes:
A new family of CMOS inverter-based OTAs for biomedical and healthcare applications. Integr. 71: 38-48 (2020) - [j14]Ricardo Póvoa, Richa Arya, António Canelas, Fábio Passos, Ricardo Martins, Nuno Lourenço, Nuno Horta:
Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications. Microelectron. J. 95 (2020) - [j13]António Canelas, Ricardo Póvoa, Ricardo Martins, Nuno Lourenço, Jorge Guilherme, João Paulo Carvalho, Nuno Horta:
FUZYE: A Fuzzy c-Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 1-13 (2020) - [j12]Ricardo Póvoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes:
A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(2): 230-234 (2020)
2010 – 2019
- 2019
- [j11]Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta:
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 989-1002 (2019) - [c19]Daniel Guerra, António Canelas, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins:
Artificial Neural Networks as an Alternative for Automatic Analog IC Placement. SMACD 2019: 1-4 - [c18]Nuno Lourenço, Engin Afacan, Ricardo Martins, Fábio Passos, António Canelas, Ricardo Póvoa, Nuno Horta, Günhan Dündar:
Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing. SMACD 2019: 13-16 - [c17]Ricardo Póvoa, António Canelas, Ricardo Martins, Nuno Horta, Nuno Lourenço, João Goes:
A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers. SMACD 2019: 161-164 - [c16]Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Póvoa, Nuno Horta, Emmanuel Moutaye:
Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization. SMACD 2019: 285-288 - 2018
- [j10]João Baúto, António Canelas, Rui Ferreira Neves, Nuno Horta:
Parallel SAX/GA for financial pattern matching using NVIDIA's GPU. Expert Syst. Appl. 105: 77-88 (2018) - [j9]Fábio Passos, Ricardo Martins, Nuno Lourenço, Elisenda Roca, Ricardo Povoa, António Canelas, Rafael Castro-López, Nuno Horta, Francisco V. Fernández:
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology. Integr. 63: 351-361 (2018) - [j8]Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Cavaco Gomes Horta, João Goes:
Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement. IEEE Trans. Circuits Syst. II Express Briefs 65-II(3): 266-270 (2018) - [j7]Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes:
Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1599-1603 (2018) - [c15]António Canelas, Ricardo Povoa, Ricardo M. F. Martins, Nuno Lourenço, Jorge Guilherme, Nuno Horta:
A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications. SMACD 2018: 1-4 - [c14]Fábio Passos, Ricardo Martins, Nuno C. Lourenço, Elisenda Roca, Rafael Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández:
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs. SMACD 2018: 1-164 - [c13]Nuno Lourenço, Joao Rosa, Ricardo Martins, Helena Aidos, António Canelas, Ricardo Povoa, Nuno Horta:
On the Exploration of Promising Analog IC Designs via Artificial Neural Networks. SMACD 2018: 133-136 - 2017
- [j6]Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta:
Stochastic-based placement template generator for analog IC layout-aware synthesis. Integr. 58: 485-495 (2017) - [c12]António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta:
Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing. DATE 2017: 1201-1206 - [c11]Nuno C. Lourenço, Ricardo Martins, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization. SMACD 2017: 1-4 - [c10]Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks. SMACD 2017: 1-4 - [c9]Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno C. G. Horta:
Systematic design of a voltage controlled oscillator using a layout-aware approach. SMACD 2017: 1-4 - 2016
- [j5]Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Povoa, Nuno Horta:
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation. Integr. 55: 316-329 (2016) - [j4]Mrinalinee Pandey, António Canelas, Ricardo Póvoa, Jorge Alves Torres, João Costa Freire, Nuno Lourenço, Nuno Horta:
Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer. Integr. 55: 330-340 (2016) - [c8]Ricardo Martins, António Canelas, Nuno Lourenço, Nuno Horta:
On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies. SMACD 2016: 1-4 - [c7]António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta:
Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations. SMACD 2016: 1-4 - 2015
- [j3]Nuno Lourenço, António Canelas, Ricardo Povoa, Ricardo Martins, Nuno Horta:
Floorplan-aware analog IC sizing and optimization based on topological constraints. Integr. 48: 183-197 (2015) - [c6]Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta:
Extraction and application of wiring symmetry rules to route analog multiport terminals. ISCAS 2015: 1945-1948 - 2014
- [j2]Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta:
Electromigration-aware analog Router with multilayer multiport terminal structures. Integr. 47(4): 532-547 (2014) - [c5]Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta:
Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures. DATE 2014: 1-6 - [c4]Ricardo Povoa, Ricardo Lourenco, Nuno Lourenço, António Canelas, Ricardo Martins, Nuno Horta:
LC-VCO automatic synthesis using multi-objective evolutionary techniques. ISCAS 2014: 293-296 - 2013
- [j1]António Canelas, Rui Ferreira Neves, Nuno Horta:
A SAX-GA approach to evolve investment strategies on financial markets based on pattern discovery techniques. Expert Syst. Appl. 40(5): 1579-1590 (2013) - [c3]Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta:
Multi-port multi-terminal analog router based on an evolutionary optimization kernel. IEEE Congress on Evolutionary Computation 2013: 2789-2796 - [c2]António Canelas, Rui Ferreira Neves, Nuno Horta:
Multi-dimensional pattern discovery in financial time series using sax-ga with extended robustness. GECCO (Companion) 2013: 179-180 - 2012
- [c1]António Canelas, Rui Ferreira Neves, Nuno Horta:
A new SAX-GA methodology applied to investment strategies optimization. GECCO 2012: 1055-1062
Coauthor Index
aka: Nuno C. Lourenço
aka: Ricardo M. F. Martins
aka: Ricardo Póvoa
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