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ORCIDJordi Tubella
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2020 – today
- 2024
[c26]Mojtaba Abaie Shoushtary
, José-María Arnau, Jordi Tubella Murgadas, Antonio González:
Memento: An Adaptive, Compiler-Assisted Register File Cache for GPUs. ISCA 2024: 978-990- [i2]Mojtaba Abaie Shoushtary, Jordi Tubella Murgadas, Antonio González:
Control Flow Management in Modern GPUs. CoRR abs/2407.02944 (2024) - 2023
- [c25]Mojtaba Abaie Shoushtary, José-María Arnau, Jordi Tubella Murgadas, Antonio González:
Lightweight Register File Caching in Collector Units for GPUs. GPGPU@PPoPP 2023: 27-33 - [i1]Mojtaba Abaie Shoushtary, José-María Arnau, Jordi Tubella Murgadas, Antonio González:
A Lightweight, Compiler-Assisted Register File Cache for GPGPU. CoRR abs/2310.17501 (2023)
2010 – 2019
- 2018
- [j5]Hamid Tabani, José-María Arnau, Jordi Tubella, Antonio González:
Performance Analysis and Optimization of Automatic Speech Recognition. IEEE Trans. Multi Scale Comput. Syst. 4(4): 847-860 (2018) - [c24]Hamid Tabani, José-María Arnau, Jordi Tubella, Antonio González:
A Novel Register Renaming Technique for Out-of-Order Processors. HPCA 2018: 259-270 - 2017
- [j4]Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Jordi Tubella, Antonio González, Lieven Eeckhout:
Shared resource aware scheduling on power-constrained tiled many-core processors. J. Parallel Distributed Comput. 100: 30-41 (2017) - [c23]Hamid Tabani, José-María Arnau, Jordi Tubella, Antonio González:
An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech Recognition. PACT 2017: 41-52 - 2016
- [c22]Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Jordi Tubella, Antonio González, Lieven Eeckhout:
Shared resource aware scheduling on power-constrained tiled many-core processors. Conf. Computing Frontiers 2016: 365-368 - 2015
- [c21]Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Trevor E. Carlson, Kenzo Van Craeynest, Jordi Tubella, Antonio González, Lieven Eeckhout:
Chrysso: an integrated power manager for constrained many-core processors. Conf. Computing Frontiers 2015: 19:1-19:8 - 2012
- [c20]Govind Sreekar Shenoy, Jordi Tubella, Antonio González:
Hardware/Software Mechanisms for Protecting an IDS against Algorithmic Complexity Attacks. IPDPS Workshops 2012: 1190-1196 - [c19]Govind Sreekar Shenoy, Jordi Tubella, Antonio González:
Exploiting temporal locality in network traffic using commodity multi-cores. ISPASS 2012: 110-111 - [c18]Govind Sreekar Shenoy, Jordi Tubella, Antonio González:
Improving the Performance Efficiency of an IDS by Exploiting Temporal Locality in Network Traffic. MASCOTS 2012: 439-448 - [c17]Govind Sreekar Shenoy, Jordi Tubella, Antonio González:
Improving the Resilience of an IDS against Performance Throttling Attacks. SecureComm 2012: 167-184 - 2011
- [c16]Govind Sreekar Shenoy, Jordi Tubella, Antonio González:
A Performance and Area Efficient Architecture for Intrusion Detection Systems. IPDPS 2011: 301-310
2000 – 2009
- 2005
- [c15]Carlos Molina, Antonio González, Jordi Tubella:
Compiler analysis for trace-level speculative multithreaded architectures. Interaction between Compilers and Computer Architectures 2005: 2-10 - [c14]Carlos Molina, Jordi Tubella, Antonio González:
Reducing Misspeculation Penalty in Trace-Level Speculative Multithreaded Architectures. ISHPC 2005: 43-55 - 2004
- [j3]Pedro Marcuello, Antonio González, Jordi Tubella:
Thread Partitioning and Value Prediction for Exploiting Speculative Thread-Level Parallelism. IEEE Trans. Computers 53(2): 114-125 (2004) - 2003
- [c13]Carles Aliagas, Carlos Molina, Montse Garcia, Antonio González, Jordi Tubella:
Value Compression to Reduce Power in Data Caches. Euro-Par 2003: 616-622 - [c12]Carlos Molina, Carles Aliagas, Montse Garcia, Antonio González, Jordi Tubella:
Non redundant data cache. ISLPED 2003: 274-277 - 2002
- [c11]Carlos Molina, Antonio González, Jordi Tubella:
Trace-Level Speculative Multithreaded Architecture. ICCD 2002: 402-407
1990 – 1999
- 1999
- [c10]Carlos Molina, Antonio González, Jordi Tubella:
Reducing Memory Traffic Via Redundant Store Instructions. HPCN Europe 1999: 1246-1249 - [c9]Antonio González, Jordi Tubella, Carlos Molina:
Trace-Level Reuse. ICPP 1999: 30-39 - [c8]Carlos Molina, Antonio González, Jordi Tubella:
Dynamic removal of redundant computations. International Conference on Supercomputing 1999: 474-481 - [c7]Pedro Marcuello, Jordi Tubella, Antonio González:
Value Prediction for Speculative Multithreaded Architectures. MICRO 1999: 230-236 - 1998
- [c6]Jordi Tubella, Antonio González:
Control Speculation in Multithreaded Processors through Dynamic Loop Detection. HPCA 1998: 14-23 - [c5]Pedro Marcuello, Antonio González, Jordi Tubella:
Speculative Multithreaded Processors. International Conference on Supercomputing 1998: 77-84 - 1996
- [b1]Jordi Tubella:
Multipath: un sistema para la programación lógica. Polytechnic University of Catalonia, Spain, 1996 - [j2]Jordi Tubella, Antonio González, E. Elias:
The Multipath Architecture for Prolog Programs. Comput. J. 39(9): 780-792 (1996) - 1995
- [c4]Jordi Tubella, Antonio González:
Exploiting path parallelism in logic programming. PDP 1995: 164-173 - 1994
- [c3]Jordi Tubella, Antonio González:
Combining depth-first and breadth-first search in Prolog execution. GULP-PRODE (2) 1994: 452-453 - [c2]Jordi Tubella, Antonio González:
A Partial Breadth-First Execution Model for Prolog. ICTAI 1994: 129-137 - [c1]Antonio González, Jordi Tubella:
The Multipath Parallel Execution Model for Prolog. PASCO 1994: 164-173 - 1993
- [j1]Jordi Tubella, Antonio González:
MEM: A new execution model for Prolog. Microprocess. Microprogramming 39(2-5): 83-86 (1993)
Coauthor Index
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last updated on 2024-10-07 21:24 CEST by the dblp team
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