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ORCIDZhangcai Huang
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2010 – 2019
- 2014
[j17]Li Ding, Zhangcai Huang, Atsushi Kurokawa, Jing Wang, Yasuaki Inoue:
An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(5): 1059-1074 (2014)- 2013
- [c10]Li Ding, Jing Wang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue:
An analytical model of the overshooting effect for multiple-input gates in nanometer technologies. ISCAS 2013: 1712-1715 - 2012
- [j16]Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue:
Modeling the Overshooting Effect of Multi-Input gate in Nanometer Technologies. J. Circuits Syst. Comput. 21(6) (2012) - [c9]Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue:
A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model. ISCAS 2012: 938-941 - 2011
- [j15]Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Qiang Li, Bin Lin, Yasuaki Inoue:
A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(5): 1201-1209 (2011) - [c8]Zhangcai Huang, Yasuaki Inoue:
A sub-100nA power management system for wireless structure health monitoring applications. ISCAS 2011: 2897-2900 - 2010
- [j14]Xuliang Zhang, Zhangcai Huang, Juebang Yu:
Memristor Model for SPICE. IEICE Trans. Electron. 93-C(3): 355-360 (2010) - [j13]Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto
, Takashi Sato, Minglu Jiang, Yasuaki Inoue:
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 250-260 (2010) - [c7]Qiang Li, Renyuan Zhang, Zhangcai Huang, Yasuaki Inoue:
A low voltage CMOS rectifier for wirelessly powered devices. ISCAS 2010: 873-876 - [c6]Zhangcai Huang, Qin Luo, Yasuaki Inoue:
A CMOS Sub-l-V nanopower current and voltage reference with leakage compensation. ISCAS 2010: 4069-4072
2000 – 2009
- 2009
- [j12]Zhangcai Huang, Minglu Jiang, Yasuaki Inoue:
A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback. IEICE Trans. Electron. 92-C(6): 806-814 (2009) - [j11]Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Shuai Fang, Yasuaki Inoue:
Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(10): 2531-2539 (2009) - 2007
- [j10]Zhangcai Huang, Yasuaki Inoue, Hong Yu, Jun Pan, Yun Yang, Quan Zhang, Shuai Fang:
Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 732-740 (2007) - [j9]Jun Pan, Yasuaki Inoue, Zheng Liang, Zhangcai Huang, Weilun Huang:
A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 748-755 (2007) - [j8]Hong Yu, Yasuaki Inoue, Kazutoshi Sako, Xiaochuan Hu, Zhangcai Huang:
An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(10): 2124-2131 (2007) - [c5]Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue:
Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies. ASP-DAC 2007: 565-570 - 2006
- [j7]Zhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue:
Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 840-846 (2006) - [j6]Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda:
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 847-855 (2006) - [j5]Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue:
Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 856-864 (2006) - [j4]Hong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang:
An Effective Pseudo-Transient Algorithm for Finding Dc Solutions of Nonlinear Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(10): 2724-2731 (2006) - [c4]Zhangcai Huang, Yasuaki Inoue, Hong Yu, Quan Zhang:
A Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback. APCCAS 2006: 708-711 - [c3]Zhangcai Huang, Yasuaki Inoue, Quan Zhang, Yuehu Zhou, Long Xie, Harutoshi Ogai:
Behavioral macromodeling of analog LSI implementation for automobile intake system. ISCAS 2006 - [c2]Hong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang:
An effective pseudo-transient algorithm for finding DC operating points of nonlinear circuits. ISCAS 2006 - 2005
- [j3]Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao:
A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(10): 2562-2569 (2005) - [j2]Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue:
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3367-3374 (2005) - [j1]Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda:
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3453-3462 (2005) - [c1]Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue:
Effective capacitance for gate delay with RC loads. ISCAS (3) 2005: 2795-2798
Coauthor Index
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