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ORCIDMasaki Kumanoya
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1990 – 1999
- 1999
[j4]Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada:
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits 34(4): 494-501 (1999)- 1996
- [j3]Katsumi Dosaka, Akira Yamazaki, Naoya Watanabe, Hideaki Abe, Jun Ohtani, Toshiyuki Ogawa, Kazunori Ishihara, Masaki Kumanoya:
A 90-MHz 16-Mb system integrated memory with direct interface to CPU. IEEE J. Solid State Circuits 31(4): 537-545 (1996) - 1995
- [j2]Masaki Kumanoya, Toshiyuki Ogawa, Kazunari Inoue:
Advances in DRAM interfaces. IEEE Micro 15(6): 30-36 (1995) - 1994
- [c1]Yasuhiro Konishi, Toshiyuki Ogawa, Masaki Kumanoya:
Testing 256k Word x 16 Bit Cache DRAM (CDRAM). ITC 1994: 360
1980 – 1989
- 1989
- [j1]Yasuhiro Konishi, Masaki Kumanoya, Hiroyuki Yamasaki, Katsumi Dosaka, Tsutomu Yoshihara:
Analysis of coupling noise between adjacent bit lines in megabit DRAMs. IEEE J. Solid State Circuits 24(1): 35-42 (1989)
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