default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDFearghal Morgan
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2023
[c36]Fearghal Morgan
, John Patrick Byrne, Abishek Bupathi, Roshan George, Muhammad Adnan Elahi, Frank Callaly, Sean Kelly, Declan O'Loughlin:
HDLGen-ChatGPT Case Study: RISC-V Processor VHDL and Verilog Model - Testbench and EDA Project Generation. RSP 2023: 11:1-11:7- 2021
- [c35]Fearghal Morgan, Arthur Beretta, Ian Gallivan, Joseph Clancy, Frédéric Rousseau, Roshan George, László Bakó, Frank Callaly:
RISC-V Online Tutor. REV 2021: 131-143
2010 – 2019
- 2018
- [j13]Gorka Epelde, Fearghal Morgan, Andoni Mujika, Frank Callaly, Peter Leskovský, Brian McGinley, Roberto Álvarez, Axel W. Blau, Finn Krewer:
Web-Based Interfaces for Virtual C. elegans Neuron Model Definition, Network Configuration, Behavioral Experiment Definition and Experiment Results Visualization. Frontiers Neuroinformatics 12: 80 (2018) - [c34]Fearghal Morgan, Declan O'Loughlin, Jeremy Audiger, Yohan Boyer, Frank Callaly:
viciLogic2.0 Online Learning and Prototyping Using PYNQ. FPL 2018: 459-460 - [c33]Fearghal Morgan, Declan O'Loughlin, Jeremy Audiger, Yohan Boyer, Niall Timlin-Canning, Krzysztof Kepa, Seamus Cawley, Ian Gallivan, László Bakó, Frank Callaly:
Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC. RSP 2018: 76-82 - 2017
- [j12]Sandeep Pande, Fearghal Morgan, Finn Krewer, Jim Harkin, Liam McDaid, Brian McGinley:
Rapid application prototyping for hardware modular spiking neural network architectures. Neural Comput. Appl. 28(9): 2767-2779 (2017) - [c32]László Bakó, Szabolcs Hajdú, Fearghal Morgan:
Evaluation and Comparison of Low FPGA Footprint, Embedded Soft-Core Processors. MACRo 2017: 23-30 - 2016
- [c31]Robert Moni, László Bakó, Szabolcs Hajdú, Fearghal Morgan, Sándor-Tihamér Brassai:
Embedded Real-time Implementation of a Computational Efficient Optical Flow Extraction Method for Intelligent Robot Control Applications. AICS 2016: 116-127 - [c30]George Martin, Jim Harkin, Liam McDaid, John J. Wade, Junxiu Liu, Fearghal Morgan:
Astrocyte to spiking neuron communication using Networks-on-Chip ring topology. SSCI 2016: 1-8 - 2015
- [c29]Fearghal Morgan, Finn Krewer, Frank Callaly, Aedan Coffey, Brian Mc Ginley:
Web-enabled Neuron Model Hardware Implementation and Testing. NEUROTECHNIX 2015: 138-145 - 2014
- [c28]Axel W. Blau, Frank Callaly, Seamus Cawley, Aedan Coffey, Alessandro De Mauro, Gorka Epelde, Lorenzo Ferrara, Finn Krewer, Carlo Liberale, Pedro Machado, Gregory Maclair, Thomas Martin McGinnity, Fearghal Morgan, Andoni Mujika, Alessandro Petrushin, Gautier Robin, John J. Wade:
The Si elegans Project - The Challenges and Prospects of Emulating Caenorhabditis elegans. Living Machines 2014: 436-438 - [c27]Finn Krewer, Aedan Coffey, Frank Callaly, Fearghal Morgan:
Neuron Models in FPGA Hardware - A Route from High Level Descriptions to Hardware Implementations. NEUROTECHNIX 2014: 177-183 - [c26]Axel W. Blau, Frank Callaly, Seamus Cawley, Aedan Coffey, Alessandro De Mauro, Gorka Epelde, Lorenzo Ferrara, Finn Krewer, Carlo Liberale, Pedro Machado, Gregory Maclair, Thomas Martin McGinnity, Fearghal Morgan, Andoni Mujika, Alexey Petrushin, Gautier Robin, John J. Wade:
Exploring Neural Principles with Si elegans, a Neuromimetic Representation of the Nematode Caenorhabditis elegans. NEUROTECHNIX 2014: 189-194 - 2013
- [j11]Sandeep Pande, Fearghal Morgan, Seamus Cawley, Tom M. Bruintjes, Gerard J. M. Smit, Brian McGinley, Snaider Carrillo, Jim Harkin, Liam McDaid:
Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network. Neural Process. Lett. 38(2): 131-153 (2013) - [j10]Sandeep Pande, Fearghal Morgan, Gerard J. M. Smit, Tom M. Bruintjes, Jochem H. Rutgers, Brian McGinley, Seamus Cawley, Jim Harkin, Liam McDaid:
Fixed latency on-chip interconnect for hardware spiking neural network architectures. Parallel Comput. 39(9): 357-371 (2013) - [j9]Snaider Carrillo, Jim Harkin, Liam McDaid, Fearghal Morgan, Sandeep Pande, Seamus Cawley, Brian McGinley:
Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations. IEEE Trans. Parallel Distributed Syst. 24(12): 2451-2461 (2013) - [c25]John Maher, Fearghal Morgan, Colm O'Riordan, Brian McGinley:
The Influence of Cell Type on Artificial Development. ECAL 2013: 446-453 - 2012
- [j8]Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep Pande, Seamus Cawley, Brian McGinley, Fearghal Morgan:
Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers. Neural Networks 33: 42-57 (2012) - [j7]Fearghal Morgan, Seamus Cawley, David Newell:
Remote FPGA Lab for Enhancing Learning of Digital Systems. ACM Trans. Reconfigurable Technol. Syst. 5(3): 18:1-18:13 (2012) - [c24]Snaider Carrillo, Jim Harkin, L. J. McDaid, Sandeep Pande, Seamus Cawley, Brian McGinley, Fearghal Morgan:
Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations. NOCS 2012: 83-90 - 2011
- [j6]Seamus Cawley, Fearghal Morgan, Brian McGinley, Sandeep Pande, Liam McDaid, Snaider Carrillo, Jim Harkin:
Hardware spiking neural network prototyping and application. Genet. Program. Evolvable Mach. 12(3): 257-280 (2011) - [j5]Brian McGinley, John Maher, Colm O'Riordan, Fearghal Morgan:
Maintaining Healthy Population Diversity Using Adaptive Crossover, Mutation, and Selection. IEEE Trans. Evol. Comput. 15(5): 692-714 (2011) - [c23]Krzysztof Kepa, Fearghal Morgan, Peter Athanas:
ERDB: An Embedded Routing Database for Reconfigurable Systems. FPL 2011: 195-200 - [c22]Fearghal Morgan, Seamus Cawley, Frank Callaly, Shane Agnew, Patrick Rocke, Martin O'Halloran, Nina Drozd, Krzysztof Kepa, Brian McGinley:
Remote FPGA Lab with Interactive Control and Visualisation Interface. FPL 2011: 496-499 - [c21]Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep Pande, Seamus Cawley, Fearghal Morgan:
Adaptive Routing Strategies for Large Scale Spiking Neural Network Hardware Implementations. ICANN (1) 2011: 77-84 - [c20]Sandeep Pande, Fearghal Morgan, Seamus Cawley, Brian McGinley, Jim Harkin, Snaider Carrillo, Liam McDaid:
Addressing the Hardware Resource Requirements of Network-on-chip based Neural Architectures. IJCCI (NCTA) 2011: 128-137 - [c19]Fearghal Morgan, Seamus Cawley:
Enhancing learning of digital systems using a remote FPGA lab. ReCoSoC 2011: 1-8 - 2010
- [j4]Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Tomasz Surmacz:
SeReCon: a secure reconfiguration controller for self-reconfigurable systems. Int. J. Crit. Comput. Based Syst. 1(1/2/3): 86-103 (2010) - [j3]Roger F. Woods, Jürgen Becker, Peter Athanas, Fearghal Morgan:
Guest Editorial ARC 2009. ACM Trans. Reconfigurable Technol. Syst. 4(1): 1:1-1:2 (2010) - [j2]Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker:
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems. ACM Trans. Reconfigurable Technol. Syst. 4(1): 4:1-4:26 (2010) - [c18]Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep Pande, Fearghal Morgan:
An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations. ICES 2010: 133-144 - [c17]Sandeep Pande, Fearghal Morgan, Seamus Cawley, Brian McGinley, Snaider Carrillo, Jim Harkin, Liam McDaid:
EMBRACE-SysC for analysis of NoC-based Spiking Neural Network architectures. SoC 2010: 139-145 - [e2]Phaophak Sirisuk, Fearghal Morgan, Tarek A. El-Ghazawi, Hideharu Amano:
Reconfigurable Computing: Architectures, Tools and Applications, 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010. Proceedings. Lecture Notes in Computer Science 5992, Springer 2010, ISBN 978-3-642-12132-6 [contents]
2000 – 2009
- 2009
- [j1]Jim Harkin, Fearghal Morgan, Liam McDaid, Steve Hall, Brian McGinley, Seamus Cawley:
A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks. Int. J. Reconfigurable Comput. 2009: 908740:1-908740:13 (2009) - [c16]Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker:
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. ARC 2009: 62-73 - [c15]John Maher, Fearghal Morgan, Oisin Mac Aodha:
Evolving plastic responses in artificial cell models. IEEE Congress on Evolutionary Computation 2009: 3018-3023 - [c14]Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz:
IP protection in Partially Reconfigurable FPGAs. FPL 2009: 403-409 - [e1]Jürgen Becker, Roger F. Woods, Peter M. Athanas, Fearghal Morgan:
Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings. Lecture Notes in Computer Science 5453, Springer 2009, ISBN 978-3-642-00640-1 [contents] - 2008
- [c13]Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Tomasz Surmacz:
SeReCon: A Trusted Environment for SoPC Design. DepCoS-RELCOMEX 2008: 332-338 - [c12]Jim Harkin, Fearghal Morgan, Steve Hall, Piotr Dudek, Thomas Dowrick, Liam McDaid:
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks. FPL 2008: 483-486 - [c11]Brian McGinley, Patrick Rocke, Fearghal Morgan, John Maher:
Reconfigurable analogue hardware evolution of adaptive spiking neural network controllers. GECCO 2008: 289-290 - [c10]Brian McGinley, Fearghal Morgan, Colm O'Riordan:
Maintaining diversity through adaptive selection, crossover and mutation. GECCO 2008: 1127-1128 - [c9]Patrick Rocke, Brian McGinley, John Maher, Fearghal Morgan, Jim Harkin:
Investigating the Suitability of FPAAs for Evolved Hardware Spiking Neural Networks. ICES 2008: 118-129 - [c8]Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Tomasz Surmacz:
SeReCon: A Secure Dynamic Partial Reconfiguration Controller. ISVLSI 2008: 292-297 - 2007
- [c7]Patrick Rocke, Brian McGinley, Fearghal Morgan, John Maher:
Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller. ARC 2007: 373-378 - [c6]Krzysztof Kosciuszkiewicz, Fearghal Morgan, Krzysztof Kepa:
Run-Time Management of Reconfigurable Hardware Tasks Using Embedded Linux. FPT 2007: 209-215 - 2006
- [c5]John Maher, Brian McGinley, Patrick Rocke, Fearghal Morgan:
Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices. FCCM 2006: 321-322 - [c4]Krzysztof Kosciuszkiewicz, Krzysztof Kepa, Fearghal Morgan:
Transparent Management of Reconfigurable Hardware in Embedded Operating Systems. ISVLSI 2006: 432-433 - 2005
- [c3]Fearghal Morgan, Patrick Rocke, Martin O'Halloran:
Applied VHDL training methodology, EDA framework and hardware implementation platform. ReConFig 2005 - [c2]Patrick Rocke, John Maher, Fearghal Morgan:
Platform for intrinsic evolution of analogue neural networks. ReConFig 2005 - 2001
- [c1]Peter McCurry, Fearghal Morgan, Liam Kilmartin:
Xilinx FPGA implementation of an image classifier for object detection applications. ICIP (3) 2001: 346-349
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 21:13 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
