default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDMicroprocessors and Microsystems, Volume 51
Volume 51, June 2017
- Miroslav Hagara, Radovan Stojanovic, Peter Kubinec, Oldrich Ondrácek:
Localization of moving edge with sub-pixel accuracy in 1-D images and its FPGA implementation. 1-7 - Yuan-Shin Hwang, Wei-Che Hsu:
Floating accumulator architecture. 8-17 - Sani Abba, Jeong-A Lee:
Bio-inspired self-aware fault-tolerant routing protocol for network-on-chip architectures using Particle Swarm Optimization. 18-38 - Kim Grüttner, Ralph Görgen, Sören Schreiner, Fernando Herrera, Pablo Peñil
, Julio L. Medina, Eugenio Villar, Gianluca Palermo, William Fornaciari, Carlo Brandolese, Davide Gadioli, Emanuele Vitali, Davide Zoni, Sara Bocchio, Luca Ceva, Paolo Azzoni, Massimo Poncino, Sara Vinco, Enrico Macii, Salvatore Cusenza, John M. Favaro, Raúl Valencia, Ingo Sander, Kathrin Rosvall, Nima Khalilzad, Davide Quaglia:
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties. 39-55 - Rajul Bansal, Abhijit Karmakar:
Efficient integration of coprocessor in LEON3 processor pipeline for System-on-Chip design. 56-75 - Arghavan Asad, Ozcan Ozturk, Mahmood Fathy, Mohammad Reza Jahed-Motlagh:
Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy. 76-98 - Yury S. Bekhtin, Pavel V. Babayan, Valery V. Strotov:
Onboard FPGA-based fast estimation of point object coordinates for linear IR-sensor. 99-105 - Andjela Draganic, Irena Orovic, Srdjan Stankovic, Xiumei Li, Zhi Wang:
An approach to classification and under-sampling of the interfering wireless signals. 106-113 - Roel Jordans, Lech Józwiak, Henk Corporaal, Rosilde Corvino:
Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project. 114-133 - Jenita Priya Rajamanickam Manokaran, Mohammed A. S. Khalid:
Experimental evaluation and comparison of two recent Network-on-Chip routers for FPGAs. 134-141 - Behzad Salami, Gorker Alp Malazgirt, Oriol Arcas-Abella, Arda Yurdakul, Nehir Sönmez:
AxleDB: A novel programmable query processing platform on FPGA. 142-164 - Fengkai Yuan, Zhenzhou Ji, Zhongchuan Fu:
RACMan: Replication-aware cache management for manycore CMPs with private LLCs. 165-175 - Milad Sangsefidi, Dariush Abedi, Ghassem Jaberipur:
Radix-8 full adder in QCA with single clock-zone carry propagation delay. 176-184 - Sara Zermani, Catherine Dezan, Chabha Hireche, Reinhardt Euler, Jean-Philippe Diguet:
Embedded context aware diagnosis for a UAV SoC platform. 185-197 - Tullio Facchinetti, Guido Benetti, Alessandro Tramonte, Luca Carraro, Alessandro Rubini, Mauro Benedetti, Enrico Maria Randone, Marcello Simonetta, Giorgio Capelli, Kimmo Keränen, Arto Ylisaukko-oja, Angelo Consoli, Jaouhar Ayadi, Guido Giuliani:
Luminous tiles: A new building device for smart architectures and applications. 198-208 - Jorge L. Tonfat, Lucas A. Tambara, André Santos, Fernanda Lima Kastensmidt:
Soft error susceptibility analysis methodology of HLS designs in SRAM-based FPGAs. 209-219 - Vojtech Miskovský, Hana Kubátová, Martin Novotný:
Influence of passive hardware redundancy on differential power analysis resistance of AES cipher implemented in FPGA. 220-226 - José L. Núñez-Yáñez:
Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors. 227-238 - Bilal Habib, Kris Gaj:
A comprehensive set of schemes for PUF response generation. 239-251 - Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Qiang Li, Guangjun Li, Axel Jantsch:
Minimizing the system impact of router faults by means of reconfiguration and adaptive routing. 252-263 - Leonardo Pereira Santos, Gabriel L. Nazar, Luigi Carro:
Exploring redundancy granularities to repair real-time FPGA-based systems. 264-274 - Marlon Wijeyasinghe, David Thomas:
Combining hardware and software codecs to enhance data channels in FPGA streaming systems. 275-288 - Mehrija Hasicic, Damir Bilic, Harun Siljak:
Criteria for Solar Car Optimized Route Estimation. 289-296 - Chun-Hsian Huang, Chien-Yu Wang, Pao-Ann Hsiung:
Elastic superposition task mapping for NoC-based reconfigurable systems. 297-312 - Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay:
Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware. 313-330 - Khalid Javeed, Xiaojun Wang, Mike Scott:
High performance hardware support for elliptic curve cryptography over general prime field. 331-342 - Ashish Mishra, Mohit Agarwal, Abhijit Rameshwar Asati, Kota Solomon Raju:
Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems. 343-355 - Yahya T. Qassim, Tim R. H. Cutmore, David D. Rowlands:
FPGA implementation of wavelet coherence for EEG and ERP signals. 356-365 - A. V. AnanthaLakshmi, Gnanou Florence Sudha:
A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications. 366-385
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-18 01:02 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
