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ORCID38th VTS 2020: San Diego, CA, USA
- 38th IEEE VLSI Test Symposium, VTS 2020, San Diego, CA, USA, April 5-8, 2020. IEEE 2020, ISBN 978-1-7281-5359-9
- Yigit Tuncel
, Ganapati Bhat, Ümit Y. Ogras:
Special Session: Physically Flexible Devices for Health and Activity Monitoring: Challenges from Design to Test. 1-5 - Wendong Wang, Ujjwal Guin, Adit D. Singh:
A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture. 1-6 - Soumya Mittal, R. D. Shawn Blanton:
A Deterministic-Statistical Multiple-Defect Diagnosis Methodology. 1-6 - Mustafa Munawar Shihab, Bharath Ramanidharan, Suraag Sunil Tellakula, Gaurav Rajavendra Reddy, Jingxiang Tian, Carl Sechen, Yiorgos Makris:
ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric. 1-6 - Xingyi Wang, Li Jiang, Krishnendu Chakrabarty:
LSTM-based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault Detection. 1-6 - Yu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jeffrey Mayer:
Effective Design of Layout-Friendly EDT Decompressor. 1-6 - Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao:
CNN-based Stochastic Regression for IDDQ Outlier Identification. 1-6 - Zizhen Liu, Jing Ye, Xing Hu, Huawei Li, Xiaowei Li, Yu Hu:
Sequence Triggered Hardware Trojan in Neural Network Accelerator. 1-6 - Dong Xiang, Jiaming Cai, Bo Liu:
Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay Testing. 1-6 - Sreejit Chakravarty, Fei Su, Indira A. Gohad, Sudheer V. Bandana, B. S. Adithya, Wei Ming Lim:
Internal I/O Testing: Definition and a Solution. 1-6 - Tong-Yu Hsieh, Pin-Xuan Wu, Chun-Chao Cheng:
On Classification of Acceptable Images for Reliable Artificial Intelligence Systems: A Case Study on Pedestrian Detection. 1-6 - Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi:
ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links. 1-6 - Shervin Roshanisefat, Hadi Mardani Kamali, Kimia Zamiri Azar, Sai Manoj Pudukotai Dinakarrao, Naghmeh Karimi, Houman Homayoun, Avesta Sasan:
DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain. 1-6 - Jiafeng Xie, Kanad Basu, Kris Gaj, Ujjwal Guin:
Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography. 1-10 - Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone:
A dynamic reconfiguration mechanism to increase the reliability of GPGPUs. 1-6 - Eric Schneider, Hans-Joachim Wunderlich:
Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling. 1-6 - Brett Sparkman, Scott C. Smith, Jia Di:
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits. 1-6 - Zhen Gao, Lingling Zhang, Ruishi Han, Pedro Reviriego, Zhiqiang Li:
Reliability Evaluation of Turbo Decoders Implemented on SRAM-FPGAs. 1-6 - Marc Hutner, R. Sethuram, Bapi Vinnakota, Dave Armstrong, A. Copperhall:
Special Session: Test Challenges in a Chiplet Marketplace. 1-12 - Yang Sun, Spencer K. Millican, Vishwani D. Agrawal:
Special Session: Survey of Test Point Insertion for Logic Built-in Self-test. 1-6 - Irith Pomeranz:
Input Test Data Volume Reduction Using Seed Complementation and Multiple LFSRs. 1-6 - Abhishek Das, Nur A. Touba:
Selective Checksum based On-line Error Correction for RRAM based Matrix Operations. 1-6 - Ayush Jain, Ujjwal Guin, M. Tanjidur Rahman, Navid Asadizanjani, Danielle Duvalsaint, R. D. Shawn Blanton:
Special Session: Novel Attacks on Logic-Locking. 1-10 - Hadjer Benkraouda, Muhammad Ashif Chakkantakath, Anastasis Keliris, Michail Maniatakos:
SNIFU: Secure Network Interception for Firmware Updates in legacy PLCs. 1-6 - Maria I. Mera Collantes, Zahra Ghodsi, Siddharth Garg:
SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks. 1-6 - Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
Quantile - Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing. 1-6 - Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Annachiara Ruospo, Riccardo Mariani, Ghani Kanawati, Ernesto Sánchez, Matteo Sonza Reorda, Maksim Jenihhin, Said Hamdioui, Christian Sauer:
Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks. 1-9 - Somayeh Sadeghi Kohan, Sybille Hellebrand:
Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 1-6 - Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama:
Innovative Test Practices in Asia. 1 - Xuan Zuo, Sandeep K. Gupta:
Aging-resilient SRAM design: an end-to-end framework. 1-6 - Riccardo Cantoro, Sandro Sartoni, Matteo Sonza Reorda:
In-field Functional Test of CAN Bus Controllers. 1-6 - Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany, Andrew Lukefahr, Farimah Farahmandi, Mark M. Tehranipoor:
SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment. 1-6 - Koji Asami, Keisuke Kusunoki, Nobuhiro Shimizu, Yoshiyuki Aoki:
Ultra-Wideband Modulation Signal Measurement Using Local Sweep Digitizing Method. 1-6 - Qidong Wang, Aijiao Cui, Gang Qu, Huawei Li:
A New Secure Scan Design with PUF-based Key for Authentication. 1-6 - Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen:
Pinhole Latent Defect Modeling and Simulation for Defect-Oriented Analog/Mixed-Signal Testing. 1-6 - Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Mitigating Read Failures in STT-MRAM. 1-6 - Suriyaprakash Natarajan, Andres F. Malavasi, Pascal Andreas Meinerzhagen:
Automated Design For Yield Through Defect Tolerance. 1-6 - Irith Pomeranz:
Non-Masking Non-Robust Tests for Path Delay Faults. 1-6 - Chris Nigh, Alex Orailoglu:
Taming Combinational Trojan Detection Challenges with Self-Referencing Adaptive Test Patterns. 1-6 - Churan Tang, Pengkun Liu, Cunqing Ma, Zongbin Liu, Jingquan Ge:
Flush+Time: A High Accuracy and High Resolution Cache Attack On ARM-FPGA Embedded SoC. 1-6 - Rajendra Bishnoi, Lizhou Wu, Moritz Fieback, Christopher Münch, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori, Ying Wang, Huawei Li, Said Hamdioui:
Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis. 1-10 - Dyi-Chung Hu, Hirohito Hashimoto, Li-Fong Tseng, Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Sean Y.-S. Chen, Jwu E. Chen, Clark Liu, Andrew Yi-Ann Huang:
Innovative Practice on Wafer Test Innovations. 1 - Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng:
Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. 1-6
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