default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID10th FCCM 2002: Napa, CA, USA
- 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings. IEEE Computer Society 2002, ISBN 0-7695-1801-X
Applications I
- Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk:
Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform. 3-12 - Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong
:
A Massively Parallel RC4 Key Search Engine. 13-21 - Tulika Mitra, Tzi-cker Chiueh:
An FPGA Implementation of Triangle Mesh Decompression. 22-
Networking I
- Gordon J. Brebner:
Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. 35-44 - Todd S. Sproull, John W. Lockwood, David E. Taylor:
Control and Configuration Software for a Reconfigurable Networking Hardware Platform. 45-
Tool I
- Mihai Budiu, Mahim Mishra, Ashwin R. Bharambe, Seth Copen Goldstein:
Peer-to-Peer Hardware-Software Interfaces for Reconfigurable Fabrics. 57-66 - Oskar Mencer:
PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs. 67-76 - Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro C. Diniz:
Coarse-Grain Pipelining on Multiple FPGA Architectures. 77-
Template Matching
- Stefan Hezel, Andreas Kugel, Reinhard Männer, Dariu Gavrila:
FPGA-Based Template Matching Using Distance Transforms. 89-97 - Jörn Gause, Peter Y. K. Cheung, Wayne Luk:
Reconfigurable Shape-Adaptive Template Matching Architectures. 98-
Networking II
- Brad L. Hutchings, R. Franklin, D. Carver:
Assisting Network Intrusion Detection with Reconfigurable Hardware. 111-120 - Peter Bellows, Jaroslav Flidr, Tom Lehman, Brian Schott, Keith D. Underwood:
GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing. 121-130 - Gokhan Memik, Seda Ogrenci Memik, William H. Mangione-Smith:
Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic. 131-
Architecture I
- Greg Stitt, Brian Grattan, Jason R. Villarreal, Frank Vahid:
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy. 143-151 - Herman Schmit, Benjamin A. Levine, Benjamin Ylvisaker:
Queue Machines: Hardware Compilation in Hardware. 152-
Applications II
- Christian Plessl, Marco Platzner:
Custom Computing Machines for the Set Covering Problem. 163-172 - Benjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. Chan:
Analysis and Implementation of the Discrete Element Method Using a Dedicated Highly Parallel Architecture in Reconfigurable Computing. 173-181 - Gerhard Lienhart, Andreas Kugel, Reinhard Männer:
Using Floating-Point Arithmetic on FPGAs to Accelerate Scientific N-Body Simulations. 182-
Architecture II
- Rong Yan, Seth Copen Goldstein:
Mobile Memory: Improving Memory Locality in Very Large Reconfigurable Fabrics. 195-204 - André DeHon, Randy Huang, John Wawrzynek:
Hardware-Assisted Fast Routing. 205-
Tools II
- George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Optimum Wordlength Allocation. 219-228 - Mark L. Chang, Scott Hauck:
Précis: A Design-Time Precision Analysis Tool. 229-238 - Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi:
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems. 239-
Image Compression
- Thomas W. Fry, Scott Hauck:
Hyperspectral Image Compression on Reconfigurable Platforms. 251-260 - Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers:
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64. 261-
Poster Session 1
- Hossam A. ElGindy, Yen-Liang Shue:
On Sparse Matrix-Vector Multiplication with FPGA-Based System. 273-274 - Stephen J. Melnikoff, Steven F. Quigley, Martin J. Russell:
Implementing a Simple Continuous Speech Recognition System on an FPGA. 275-276 - Cyprian Grassmann, Joachim K. Anlauf:
RACER - A Rapid Prototyping Accelerator for Pulsed Neural Networks. 277-278 - Henry Styles, Wayne Luk:
Accelerating Radiosity Calculations Using Reconfigurable Platforms. 279-281 - N. A. Reis, José T. de Sousa:
On Implementing a Configware/Software SAT Solver. 282-283 - Jonathan E. Scalera, Creed F. Jones III, Maneesh Soni, Mark B. Bucciero, Peter M. Athanas, A. Lynn Abbott, Amitabh Mishra:
Reconfigurable Object Detection in FLIR Image Sequences. 284-285 - Marc Necker, Didier Contis, David E. Schimmel:
TCP-Stream Reassembly and State Tracking in Hardware. 286-
Poster Session 2
- João M. P. Cardoso, Markus Weinhardt:
Fast and Guaranteed C Compilation onto the PACT-XPP? Reconfigurable Computing Platform. 291-292 - Andreas Koch, Nico Kasprzyk:
Module Generators Driving the Compilation for Adaptive Computing Systems. 293-294 - Tero Rissa, Milan Vasilko, Jarkko Niittylahti:
System-Level Modelling and Implementation Technique for Run-Time Reconfigurable Systems. 295-296 - Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk:
Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign. 297-298 - J. Greg Nash:
Automatic Latency-Optimal Design of FPGA-Based Systolic Arrays. 299-300 - A. P. Wim Böhm, J. Ross Beveridge, Bruce A. Draper, Charlie Ross, Monica Chawathe, Walid A. Najjar:
Compiling ATR Probing Codes for Execution on FPGA Hardware. 301-302 - Nicholas Weaver, John Wawrzynek:
The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks. 303-
Poster Session 3
- Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba:
A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing. 307-308 - Joshua D. Walstrom, Jeffrey J. Cook, Derek B. Gottlieb, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter:
The Design of the Amalgam Reconfigurable Cluster. 309-310 - Jeffrey J. Cook, Derek B. Gottlieb, Joshua D. Walstrom, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter:
Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor. 311-
Poster Session 4
- Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi:
Customising Floating-Point Designs. 315-317 - Tim Courtney, Richard H. Turner, Roger F. Woods:
Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes. 318-
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-15 19:20 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
