default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID14th COOL Chips 2011: Yokohama, Japan
- 2011 IEEE Symposium on Low-Power and High-Speed Chips, Cool Chips XIV, Yokohama, Japan, 20-22 April, 2011. IEEE Computer Society 2011, ISBN 978-1-61284-883-9
- Takashi Yoshikawa, Fumihiko Hyuga, Masayuki Tokunaga, Yutaka Yamada, Shigehiro Asano:
FlexGrip™: A small and high-performance programmable hardware for highly sequential application. 1-3 - Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura
, Masaaki Kondo:
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. 1-3 - Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato:
An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller. 1-3 - Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi Ohkawa, Rimon Ikeno, Yukoh Matsumoto, Fumito Imura, Motohiro Suzuki, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi:
COOL interconnect low power interconnection technology for scalable 3D LSI design. 1-3 - Daejin Park, Tag Gon Kim, Chang-Min Kim, Sungho Kwak:
A low-power sync processor with a floating-point timer and universal edge tracer for 3DTV active shutter glasses. 1-3 - C. A. Court, Paul H. J. Kelly:
Loop-Directed Mothballing: Power-gating execution units using fast analysis of inner loops. 1-3 - Xiaoliang Tan, Anh-Tuan Do, Shoushun Chen, Kiat Seng Yeo, Zhi-Hui Kong:
A new match line sensing technique in Content Addressable Memory. 1-3 - Daiju Nakano, Yasuteru Kohda, Kohji Takano, Toshiyuki Yamane, Nobuyuki Ohba, Yasunao Katayama:
Multi-Gbps 60-GHz single-carrier system using a low-power coherent detection technique. 1-3 - Hideki Yamada, Toshiyuki Yamagishi, Tomoya Suzuki, Kuniaki Ito, Koji Horisaki, Tom Vander Aa, Toshio Fujisawa, Liesbet Van der Perre, Yasuo Unekawa:
A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor. 1-3 - Daisuke Taki, Tatsuo Shiozawa, Kuniaki Ito, Youichiro Shiba, Kouji Horisaki, Hirotsugu Kajihara, Toshiyuki Yamagishi, Masahiro Sekiya, Akira Yamaga, Tetsuya Fujita, Hiroyuki Hara, Masanori Kuwahara, Toshio Fujisawa, Yasuo Unekawa:
A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications. 1-3 - Masato Motomura, Takafumi Aoki, Toru Awashima, Toru Baji, Masaaki Ishikawa:
Panel discussions: Impact on society by fusion and harmony of mobile devices, servers, and networks - Their direction of evolutions and optimal roles. 1-2
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-15 20:32 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
