default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID27th ASAP 2016: London, UK
- 27th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2016, London, United Kingdom, July 6-8, 2016. IEEE Computer Society 2016, ISBN 978-1-5090-1503-0
- David Thomas, Suhaib A. Fahmy:
Message from the ASAP 2016 chairs. iii-iv - Ehsan Atoofian:
Compressed L1 data cache and L2 cache in GPGPUs. 1-8 - Anderson Luiz Sartor, Stephan Wong, Antonio C. S. Beck:
Adaptive ILP control to increase fault tolerance for VLIW processors. 9-16 - Dirmanto Jap, Wei He, Shivam Bhasin:
Supervised and unsupervised machine learning for side-channel based Trojan detection. 17-24 - Pascal Sasdrich
, Tim Güneysu:
A grain in the silicon: SCA-protected AES in less than 30 slices. 25-32 - Guoyang Chen, Huiyang Zhou, Xipeng Shen, Joshua Gahm, Narayan Venkat, Skip Booth, John Marshall:
OpenCL-based erasure coding on heterogeneous architectures. 33-40 - Haohuan Fu, Jingheng Xu, Lin Gan, Chao Yang, Wei Xue, Wenlai Zhao, Wen Shi, Xinliang Wang, Guangwen Yang:
Unleashing the performance potential of CPU-GPU platforms for the 3D atmospheric Euler solver. 41-49 - Sebastian Haas, Tomas Karnagel, Oliver Arnold, Erik Laux, Benjamin Schlegel, Gerhard P. Fettweis, Wolfgang Lehner:
HW/SW-database-codesign for compressed bitmap index processing. 50-57 - Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. 58-66 - Jian Cai, Aviral Shrivastava:
Efficient pointer management of stack data for software managed multicores. 67-74 - Jongsok Choi, Ruolong Lian, Stephen Dean Brown, Jason Helge Anderson:
A unified software approach to specify pipeline and spatial parallelism in FPGA hardware. 75-82 - Mohammad Reza Mohammadnia, Lesley Shannon:
A multi-beam Scan Mode Synthetic Aperture Radar processor suitable for satellite operation. 83-90 - David B. Thomas:
Synthesisable recursion for C++ HLS tools. 91-98 - Ben Lindsey, Matthew Leslie, Wayne Luk:
A Domain Specific Language for accelerated Multilevel Monte Carlo simulations. 99-106 - Wenlai Zhao, Haohuan Fu, Wayne Luk, Teng Yu, Shaojun Wang, Bo Feng, Yuchun Ma, Guangwen Yang:
F-CNN: An FPGA-based framework for training Convolutional Neural Networks. 107-114 - Shmuel Wimer, Israel Koren:
Energy efficient deeply fused dot-product multiplication architecture. 115-122 - Mark G. Arnold, Ed Chester, John R. Cowles:
Guarding the guards: Enhancing LNS performance for common applications. 123-130 - Justine Bonnot, Erwan Nogues, Daniel Ménard:
New non-uniform segmentation technique for software function evaluation. 131-138 - Caroline Collange, Mioara Joldes, Jean-Michel Muller, Valentina Popescu:
Parallel floating-point expansions for extended-precision GPU computations. 139-146 - Lois Orosa, Rodolfo Azevedo:
Temporal frequent value locality. 147-152 - Marcus Vinicius Duarte dos Santos, Edna Barros, Andre Aziz:
A MPSoC cache design space exploration approach based on ABC algorithm to optimize energy consumption and performance. 153-158 - Karthik Tanikella, Yohan Ko, Reiley Jeyapaul, Kyoungwoo Lee, Aviral Shrivastava:
gemV: A validated toolset for the early exploration of system reliability. 159-163 - Polydoros Petrakis, Mohammed Abuteir, Miltos D. Grammatikakis, Kyprianos Papadimitriou, Roman Obermaisser, Zaher Owda, Antonis Papagrigoriou, Michael Soulie, Marcello Coppola:
On-chip networks for mixed-criticality systems. 164-169 - Jan Christian Kässens, Lars Wienbrandt, Manfred Schimmler, Jorge González-Domínguez, Bertil Schmidt:
Combining GPU and FPGA technology for efficient exhaustive interaction analysis in GWAS. 170-175 - Tarek S. Abdelrahman:
Accelerating K-means clustering on a tightly-coupled processor-FPGA heterogeneous system. 176-181 - Lin Li, Amanullah Ghazi, Jani Boutellier, Lauri Anttila, Mikko Valkama, Shuvra S. Bhattacharyya:
Design space exploration and constrained multiobjective optimization for digital predistortion systems. 182-185 - Antonyus P. A. Ferreira, Joao G. M. Silva, Jefferson R. L. Anjos, Luiz H. A. Figueiroa, Edna Natividade da Silva Barros, Manoel Eusébio de Lima, Victor Wanderley Costa de Medeiros:
A hardware accelerator for the alignment of multiple DNA sequences in forensic identification. 186-190 - Sachille Atapattu, Namitha Liyanage, Nisal Menuka, Ishantha Perera, Ajith Pasqual:
Real time all intra HEVC HD encoder on FPGA. 191-195 - Tsvetan Shoshkov, Todor P. Stefanov, Bart Kienhuis:
Parametrized system level design: Real-time X-Ray image processing case study. 196-201 - Roberto R. Osorio:
Pipelined FPGA implementation of numerical integration of the Hodgkin-Huxley model. 202-206 - Christian Spindeldreier, Thijs J. Wendrich, Ernst Maria Rasel, Wolfgang Ertmer, Holger Blume:
FPGA-based frequency estimation of a DFB laser using Rb spectroscopy for space missions. 207-212 - Konstantinos Krommydas, Ruchira Sasanka, Wu-chun Feng:
Bridging the FPGA programmability-portability Gap via automatic OpenCL code generation and tuning. 213-218 - Tetsuo Miyauchi, Kiyofumi Tanaka:
Configuration technique for adaptability of multicore processors on FPGA. 219-220 - Jingheng Xu, Haohuan Fu, Lin Gan, Yu Song, Hongbo Peng, Wen Shi, Guangwen Yang:
Performance optimization of Jacobi stencil algorithms based on POWER8 architecture. 221-222 - Zhinan Cheng, Xi Li, Jiachen Song, Beilei Sun, Xuehai Zhou, Chao Wang:
Display power reduction for mobile closed-source games. 223-224 - Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda:
An efficient embedded processor for object detection using ASIP methodology. 225-226 - Hend Affes, Amal Ben Ameur, Michel Auguin, François Verdier, Calypso Barnes:
An ESL framework for low power architecture design space exploration. 227-228 - Jose Raul Garcia Ordaz, Dirk Koch:
soft-NEON: A study on replacing the NEON engine of an ARM SoC with a reconfigurable fabric. 229-230 - Isabela Rossales, Maximiliam Luppe:
Architecture for fractal dimension estimation based on Minkowski-Bouligand method using integer distances. 231-232 - Ahmed S. Eissa, Mahmoud A. Elmohr, Mostafa A. Saleh, Khaled E. Ahmed, Mohammed M. Farag:
SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture. 233-234 - Maria Cireno, Andre Aziz, Edna Barros:
Temporized data prefetching algorithm for NoC-based multiprocessor systems. 235-236 - Amine Ait Si Ali, Abbes Amira, Faycal Bensaali, Mohieddine Benammar, Amine Bermak:
HW/SW co-design based implementation of Gas discrimination. 237-238 - Manish Kumar Jaiswal, Hayden Kwok-Hay So:
Architecture for quadruple precision floating point division with multi-precision support. 239-240 - Cecil Accetti R. de A. Melo, Edna Barros:
Oolong: A Baseband processor extension to the RISC-V ISA. 241-242 - Teng Yu, Bo Feng, Mark Stillwell, José Gabriel F. Coutinho, Wenlai Zhao, Shuang Liang, Wayne Luk, Alexander L. Wolf, Yuchun Ma:
Relation-oriented resource allocation for multi-accelerator systems. 243-244
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-18 20:33 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
