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ORCID3DIC 2019: Sendai, Japan
- 2019 International 3D Systems Integration Conference (3DIC), Sendai, Japan, October 8-10, 2019. IEEE 2019, ISBN 978-1-7281-4870-0
- Jing Tao, Hongyu Li, Peng Zhao, Yu Dian Lim
, Anak Agung Alit Apriyana, Chuan Seng Tan:
Design Considerations and Fabrication Challenges of Surface Electrode Ion Trap with TSV Integration. 1-5 - Tsukasa Miura, Masaki Sakakibara, Hirotsugu Takahashi, Tadayuki Taura, Keiji Tatani, Yusuke Oike, Takayuki Ezaki:
A 6.9 μm Pixel-Pitch 3D Stacked Global Shutter CMOS Image Sensor with 3M Cu-Cu connections. 1-2 - Koji Sakui, Takayuki Ohba:
High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology. 1-4 - Ziyue Zhang, Yingtao Ding, Zhiming Chen, Mingrui Zhou, Lei Xiao, Ziru Cai, Miao Xiong, Xiao Gong:
Design and Evaluation of a Novel and Ultra-Compact Fully-TGV-based Self-Shielding Bandpass Filter for 5G Applications. 1-4 - Makoto Motoyoshi, Kohki Yanagimura, Taikoh Fushimi, Shunta Endo:
Stacked Pixel Sensor/Detector Technology using Au Micro-Bump Junction. 1-4 - Koutaro Hachiya, Atsushi Kurokawa:
Variability Cancellation to Improve Diagnostic Performance of Testing through Silicon Vias in Power Distribution Network of 3D-IC. 1-6 - Miho Yamada, Shun Ono, Yasuo Arai, Ikuo Kurachi, Toru Tsuboyama, Masayuki Ikebe, Makoto Motoyoshi:
3D Integrated Pixel Sensor with Silicon-on-Insulator Technology for the International Linear Collider Experiment. 1-4 - Hanna Soneda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu:
Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes. 1-5 - Wei-Hsuan Yang, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun, Shih-Hsu Huang:
A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. 1-3 - Srinivasan Gopal, Deukhyoun Heo, Tanay Karnik:
Hierarchical Design Methodology and Optimization for Proximity Communication based Contactless 3D ThruChip Interface. 1-6 - Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi:
Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core. 1-4 - Imed Jani, Didier Lattard, Pascal Vivet, Lucile Arnaud, Edith Beigné:
Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects. 1-4 - Yi-Chieh Tsai, Chia-Hsuan Lee, Kuan-Neng Chen:
Investigation of Low Temperature Cu Pillar Eutectic Bonding for 3D Chip Stacking Technology. 1-4 - Chuei-Tang Wang, Douglas Yu:
Power-Performance Advantages of InFO Technology for Advanced System Integration. 1-4 - Kei Sumita, Jun Takeyasu, Kimihiko Kato, Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi:
Fabrication of High Quality InAs-on-Lnsulator Structures by Smart Cut Process with Reuse of InAs Wafers. 1-2 - Kwang-Seong Choi, Yong-Sung Eom, Seok Hwan Moon, Jiho Joo, Kwangjoo Lee, Jung Hak Kim, Ju Hyeon Kim:
Development of Laser-Assisted Bonding with Compression (LABC) Process for 3D IC Integration. 1-3 - Demin Liu, Po-Chih Chen, Yi-Chieh Tsai, Kuan-Neng Chen:
Low Temperature Cu to Cu Direct Bonding below 150 °C with Au Passivation Layer. 1-4 - Fumihiro Inoue, Julien Bertheau, Samuel Suhard, Alain Phommahaxay, Takuya Ohashi, Tetsuro Kinoshita, Yohei Kinoshita, Eric Beyne:
Protective Layer for Collective Die to Wafer Hybrid Bonding. 1-4 - Valeriy Sukharev, Armen Kteyan, Jun-Ho Choy:
An Accurate Assessment of Chip-Package Interaction is a Key Factor for Designing Resilient 3D IC Systems. 1-6 - T. Robert Harris, W. Rhett Davis, Steven Lipa, W. Shepherd Pitts, Paul D. Franzon:
Vertical Stack Thermal Characterization of Heterogeneous Integration and Packages. 1-3 - Akira Matsuzawa:
A Universal ADC for Sensor Applications. 1-4 - Mariappan Murugesan, Mitsumasa Koyanagi, Hiroyuki Hashimoto, Ji Chel Bea, Takafumi Fukushima:
Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration. 1-4 - Akihiro Noriki, Isao Tamai, Yasuhiro Ibusuki, Akio Ukita, Satoshi Suda, Daisuke Shimura, Yosuke Onawa, Hiroki Yaegashi, Takeru Amano:
Optical TSV Using Si-Photonics Integrated Curved Micro-Mirror. 1-4 - Amadine Jouve, Loïc Sanchez, Clément Castan, Nicolas Bresson, Frank Fournel, Nicolas Raynaud, Pascal Metzger:
Die to Wafer Direct Hybid Bonding Demonstration with High Alignment Accuracy and Electrical Yields. 1-7 - Yuki Miwa, Sungho Lee, Rui Liang, Kousei Kumahara, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka:
Characterization of Low-Height Solder Microbump Bonding for Fine-Pitch Inter-Chip Connection in 3DICs. 1-4 - Giuliano Sisto, Peter Debacker, Rongmei Chen, Geert Van der Plas, Richard Chou, Eric Beyne, Dragomir Milojevic:
Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route. 1-4 - Hae-Sung Park, Han Kyeol Seo, Sarah Eunkyung Kim:
Characterization of Nitride Passivated Cu Surface for Low-Temperature Cu-Cu Bonding. 1-4 - Koji Hamaguchi, Mitsuki Nakata, Kouta Segawa, Naoya Suzuki, Toshihisa Nonaka:
Investigation of the Influence of Material Properties on Warpage and Solder Joint Reliability of 2.5D & FO Package. 1-6 - Peter Ramm, Armin Klumpp, Christof Landesberger, Josef Weber, Andy Heinig, Peter Schneider, Günter Elst, Manfred Engelhardt:
Fraunhofer's Initial and Ongoing Contributions in 3D IC Integration. 1-5 - Robert Fischbach, Tilman Horst, Jens Lienig:
A Graph-Based Model of Micro-Transfer Printing for Cost-Optimized Heterogeneous 2.5D Systems. 1-6 - Hiroto Tanaka, Yoshiyuki Arai, Toshiyuki Jinda, Noboru Asahi, Katsumi Terada:
Collective and Gang Bonding for Three-Dimensional Integrated Circuits in Chip-on-Wafer Process. 1-3 - Sreejith Kochupurackal Rajan, Ming Jui Li, Muhannad S. Bakir, Gary S. May:
High Density and Low-Temperature Interconnection Enabled by Mechanical Self-Alignment and Electroless Plating. 1-4 - Takahiro Nagata, Kazumichi Tsumura, Kenro Nakamura, Kengo Uchida, Jin Kawakita, Toyohiro Chikyow, Kazuyuki Higashi:
Photoelectroscopic Study of Mn Barrier Layer on SiO2 for Si Wafer Bonding Process. 1-4 - Taro Matsudaira, Shunsuke Shindo, Tomohiro Shimizu, Takeshi Ito, Shoso Shinguhara, Satoru Shimizu:
Cu Diffusion Barrier Properties of Various CoWB Electroless Plated Films on SiO2/Si Substrate for Via-last TSV Application. 1-4 - Akitsu Shigetou, Tilo H. Yang, C. Robert Kao:
Hydrolysis-Tolerant Hybrid Bonding in Ambient Atmosphere for 3D Integration. 1-3 - Fan-Hsuan Tang, Hsu-Yu Kao, Shih-Hsu Huang, Jin-Fu Li:
3D Test Wrapper Chain Optimization with I/O Cells Binding Considered. 1-4 - Toshiaki Satoh, Hiroyuki Yotsuyanagi, Masaki Hashizume:
On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection. 1-4 - Chia-Hsuan Lee, Hsin-Chi Chang, Jui-Han Liu, Hiroyuki Ito, Young-Suk Kim, Kuan-Neng Chen, Takayuki Ohba:
Temperature Cycling Reliability of WOW Bumpless Through Silicon Vias. 1-4 - Alit Apriyana Anak Agung, Peng Zhao, Chuan Seng Tan:
TiN Guard Ring Around TSV for Cross-Talk Suppression of Parallel Networking of Data Center. 1-4 - Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi:
Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICs. 1-3 - Mariappan Murugesan, Mitsumasa Koyanagi, Takafumi Fukushima:
Growth Optimization of Multi-Layer Graphene for Thermal-TSV Application in 3D-LSI. 1-5 - Sethavut Duangchan, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Akiyoshi Baba:
SiN used as a Stressor in Germanium-On-Insulator Substrate. 1-5 - Cheong-Ha Jung, Won Seo, Gu-sung Kim:
Thermal Stress Tracking in Multi-Die 3D Stacking Structure by Finite Element Analysis. 1-2 - Koichi Takemura, Akio Ukita, Yasuhiro Ibusuki, Mitsuru Kurihara, Akihiro Noriki, Takeru Amano, Daisuke Okamoto, Yasuyuki Suzuki, Kazuhiko Kurata:
Vertical Optical and Electrical Interconnection for Chip-Scale-Packaged Si Photonic Transceivers. 1-6 - Dimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne:
Process Complexity and Cost Considerations of Multi-Layer Die Stacks. 1-6 - Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka:
Investigation of the Underfill with Negative-Thermal-Expansion Material to Suppress Mechanical Stress in 3D Integration System. 1-4 - Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 1-4 - Rui Liang, Sungho Lee, Yuki Miwa, Kousei Kumahara, Mariappan Murugesan, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka:
Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO2 for Low-Temperature TSV Liner Formation. 1-4 - Toru Aoki, Katsuyuki Takagi, Toshiyuki Takagi, Hiroki Kase, Akifumi Koike:
X-ray Photon-Counting Imager with CdTe/Si-LSI Stacking. 1-4 - Koji Kiyoyama, Qian Zhengy, Hiroyuki Hashimoto, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka:
Development of a CDS Circuit for 3-D Stacked Neural Network Chip using CMOS Analog Signal Processing. 1-4 - Tadatomo Yamada, Ken Takano, Toshiaki Menjo, Shinya Takyu:
Study of Optimizing Stress-Strain Curve of Adhesive for High Expansion Tape. 1-4 - Emilie Bourjot, Paul Stewart, Christophe Dubarry, E. Lagoutte, E. Rolland, Nicolas Bresson, G. Romano, D. Scevola, Viorel Balan, Jérôme Dechamp, Marc Zussy, Gaëlle Mauguen, Clément Castan, Loïc Sanchez, Amadine Jouve, Frank Fournel, Séverine Cheramy:
Towards a Complete Direct Hybrid Bonding D2W Integration Flow: Known-Good-Dies and Die Planarization Modules Development. 1-5 - Timothy M. Hancock, Jeffrey C. Demmin:
Heterogeneous and 3D Integration at DARPA. 1-4 - Olivier Billoint, Karim Azizi-Mourier, Gerald Cibrario, Didier Lattard, Mehdi Mouhdach, Sébastien Thuries, Pascal Vivet:
Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations. 1-5 - Shunsuke Hanatani, Takuya Yorioka, Tomohiro Shimizu, Takeshi Ito, Shoso Shingubara:
Study of MacEtch using Additives for Preparation of TSV. 1-4 - Minami Nakayama, Seiya Abe, Satoshi Matsumoto:
Transformer-Less Floating Gate Driver for 3D Power SoC. 1-4 - Y. Kagawa, H. Iwamoto:
3D Integration Technologies for the Stacked CMOS Image Sensors. 1-4 - Jubee Tada, Kazuto Takahashi, Ryusuke Egawa:
A Design Scheme for 3-D Stacked CNN Accelerators. 1-4 - Masahide Goto, Joeri De Vos, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Eiji Higurashi, Yuki Honda, Takuya Saraya, Masaharu Kobayashi, Hiroshi Toshiyoshi, Toshiro Hiramoto:
Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers. 1-4 - Tadao Nakamura:
An Introduction to Marching Memory (MM). 1-3 - Sungho Lee, Yuki Susumago, Zhengyang Qian, Noriyuki Takahashi, Hisashi Kino, Tetsu Tanaka, Takafumi Fukushima:
Development of 3D-IC Embedded Flexible Hybrid System. 1-4 - Han Kyeol Seo, Hae-Sung Park, Sarah Eunkyung Kim:
Effects of Argon and Nitrogen ion Bombardments on Sputtered and Electroplated Cu Surfaces for Cu Bonding Application. 1-4 - Masahiro Nomura:
Heat Transfer in Nanostructured Si and Heat Flux Control Technique. 1-4 - Yoshiaki Hagiwara:
Multichip CMOS Image Sensor Structure for Flash Image Acquisition. 1-6 - Po-Chih Chen, Demin Liu, Kuan-Neng Chen:
Low-Temperature Wafer-Level Metal Bonding with Gold Thin Film at 100 °C. 1-4 - Quy Dinh, Kazuo Kondo, Tetsuji Hirato:
Reduction of TSV Pumping. 1-4 - Ken Suzuki, Ryota Mizuno, Yutaro Nakoshi, Hideo Miura:
Crystallinity Dependence of Long-Term Reliability of Electroplated Gold Thin-Film Interconnections. 1-5 - Shunji Kurooka, Yoshinori Hotta, Ai Nakamura, Mitsumasa Koyanagi, Takafumi Fukushima:
Cu-Cu Bonding Challenges with 'i-ACF' for Advanced 3D Integration. 1-4
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