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ORCIDZaid Al-bayati
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2010 – 2019
- 2019
[j4]Zaid Al-bayati
, Youcheng Sun, Haibo Zeng, Marco Di Natale, Qi Zhu, Brett H. Meyer:
Partitioning and Selection of Data Consistency Mechanisms for Multicore Real-Time Systems. ACM Trans. Embed. Comput. Syst. 18(4): 35:1-35:28 (2019)- 2018
- [j3]Jonah Caplan, Zaid Al-bayati, Haibo Zeng, Brett H. Meyer:
Mapping and Scheduling Mixed-Criticality Systems with On-Demand Redundancy. IEEE Trans. Computers 67(4): 582-588 (2018) - 2017
- [j2]Qingling Zhao, Zaid Al-bayati, Zonghua Gu, Haibo Zeng:
Optimized Implementation of Multirate Mixed-Criticality Synchronous Reactive Models. ACM Trans. Design Autom. Electr. Syst. 22(2): 23:1-23:25 (2017) - 2016
- [c7]Zaid Al-bayati, Jonah Caplan, Brett H. Meyer, Haibo Zeng:
A four-mode model for efficient fault-tolerant mixed-criticality systems. DATE 2016: 97-102 - [c6]Zaid Al-bayati, Brett H. Meyer, Haibo Zeng:
Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures. DFT 2016: 57-62 - 2015
- [c5]Zaid Al-bayati, Qingling Zhao, Ahmed Youssef, Haibo Zeng, Zonghua Gu:
Enhanced partitioned scheduling of Mixed-Criticality Systems on multicore platforms. ASP-DAC 2015: 630-635 - [c4]Zaid Al-bayati, Youcheng Sun, Haibo Zeng, Marco Di Natale, Qi Zhu, Brett H. Meyer:
Task placement and selection of data consistency mechanisms for real-time multicore applications. RTAS 2015: 172-181 - 2013
- [c3]Zaid Al-bayati, Haibo Zeng, Marco Di Natale, Zonghua Gu:
Multitask implementation of synchronous reactive models with Earliest Deadline First scheduling. SIES 2013: 168-177 - 2012
- [j1]Sa'ed Abed, Bassam Jamil Mohd, Zaid Al-bayati, Sahel Alouneh:
Low power Wallace multiplier design based on wide counters. Int. J. Circuit Theory Appl. 40(11): 1175-1185 (2012) - [c2]Zaid Al-bayati, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria:
A novel hybrid FIFO asynchronous clock domain crossing interfacing method. ACM Great Lakes Symposium on VLSI 2012: 271-274 - [c1]Zaid Al-bayati, Otmane Aït Mohamed, Yvon Savaria, Mounir Boukadoum:
Probabilistic model checking of clock domain crossing interfaces. NEWCAS 2012: 193-196
Coauthor Index
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