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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Framework and drivers for configuring and reading different PHYs
4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 */
10
11#ifndef __PHY_H
12#define __PHY_H
13
14#include <linux/compiler.h>
15#include <linux/spinlock.h>
16#include <linux/ethtool.h>
17#include <linux/leds.h>
18#include <linux/linkmode.h>
19#include <linux/netlink.h>
20#include <linux/mdio.h>
21#include <linux/mii.h>
22#include <linux/mii_timestamper.h>
23#include <linux/module.h>
24#include <linux/timer.h>
25#include <linux/workqueue.h>
26#include <linux/mod_devicetable.h>
27#include <linux/u64_stats_sync.h>
28#include <linux/irqreturn.h>
29#include <linux/iopoll.h>
30#include <linux/refcount.h>
31
32#include <linux/atomic.h>
33#include <net/eee.h>
34
35extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init;
36extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;
37extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init;
38extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
39extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;
40extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init;
41extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init;
42extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap2_features) __ro_after_init;
43
44#define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features)
45#define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features)
46#define PHY_BASIC_T1S_P2MP_FEATURES ((unsigned long *)&phy_basic_t1s_p2mp_features)
47#define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features)
48#define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features)
49#define PHY_10GBIT_FEATURES ((unsigned long *)&phy_10gbit_features)
50#define PHY_EEE_CAP1_FEATURES ((unsigned long *)&phy_eee_cap1_features)
51#define PHY_EEE_CAP2_FEATURES ((unsigned long *)&phy_eee_cap2_features)
52
53extern const int phy_basic_ports_array[3];
54
55/*
56 * Set phydev->irq to PHY_POLL if interrupts are not supported,
57 * or not desired for this PHY. Set to PHY_MAC_INTERRUPT if
58 * the attached MAC driver handles the interrupt
59 */
60#define PHY_POLL -1
61#define PHY_MAC_INTERRUPT -2
62
63#define PHY_IS_INTERNAL 0x00000001
64#define PHY_RST_AFTER_CLK_EN 0x00000002
65#define PHY_POLL_CABLE_TEST 0x00000004
66#define PHY_ALWAYS_CALL_SUSPEND 0x00000008
67#define MDIO_DEVICE_IS_PHY 0x80000000
68
69/**
70 * enum phy_interface_t - Interface Mode definitions
71 *
72 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch
73 * @PHY_INTERFACE_MODE_INTERNAL: No interface, MAC and PHY combined
74 * @PHY_INTERFACE_MODE_MII: Media-independent interface
75 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface
76 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface
77 * @PHY_INTERFACE_MODE_TBI: Ten Bit Interface
78 * @PHY_INTERFACE_MODE_REVMII: Reverse Media Independent Interface
79 * @PHY_INTERFACE_MODE_RMII: Reduced Media Independent Interface
80 * @PHY_INTERFACE_MODE_REVRMII: Reduced Media Independent Interface in PHY role
81 * @PHY_INTERFACE_MODE_RGMII: Reduced gigabit media-independent interface
82 * @PHY_INTERFACE_MODE_RGMII_ID: RGMII with Internal RX+TX delay
83 * @PHY_INTERFACE_MODE_RGMII_RXID: RGMII with Internal RX delay
84 * @PHY_INTERFACE_MODE_RGMII_TXID: RGMII with Internal TX delay
85 * @PHY_INTERFACE_MODE_RTBI: Reduced TBI
86 * @PHY_INTERFACE_MODE_SMII: Serial MII
87 * @PHY_INTERFACE_MODE_XGMII: 10 gigabit media-independent interface
88 * @PHY_INTERFACE_MODE_XLGMII:40 gigabit media-independent interface
89 * @PHY_INTERFACE_MODE_MOCA: Multimedia over Coax
90 * @PHY_INTERFACE_MODE_PSGMII: Penta SGMII
91 * @PHY_INTERFACE_MODE_QSGMII: Quad SGMII
92 * @PHY_INTERFACE_MODE_TRGMII: Turbo RGMII
93 * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX
94 * @PHY_INTERFACE_MODE_1000BASEX: 1000 BaseX
95 * @PHY_INTERFACE_MODE_2500BASEX: 2500 BaseX
96 * @PHY_INTERFACE_MODE_5GBASER: 5G BaseR
97 * @PHY_INTERFACE_MODE_RXAUI: Reduced XAUI
98 * @PHY_INTERFACE_MODE_XAUI: 10 Gigabit Attachment Unit Interface
99 * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR
100 * @PHY_INTERFACE_MODE_25GBASER: 25G BaseR
101 * @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII
102 * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN
103 * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII
104 * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN
105 * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII
106 * @PHY_INTERFACE_MODE_50GBASER: 50GBase-R - with Clause 134 FEC
107 * @PHY_INTERFACE_MODE_LAUI: 50 Gigabit Attachment Unit Interface
108 * @PHY_INTERFACE_MODE_100GBASEP: 100GBase-P - with Clause 134 FEC
109 * @PHY_INTERFACE_MODE_MIILITE: MII-Lite - MII without RXER TXER CRS COL
110 * @PHY_INTERFACE_MODE_MAX: Book keeping
111 *
112 * Describes the interface between the MAC and PHY.
113 */
114typedef enum {
115 PHY_INTERFACE_MODE_NA,
116 PHY_INTERFACE_MODE_INTERNAL,
117 PHY_INTERFACE_MODE_MII,
118 PHY_INTERFACE_MODE_GMII,
119 PHY_INTERFACE_MODE_SGMII,
120 PHY_INTERFACE_MODE_TBI,
121 PHY_INTERFACE_MODE_REVMII,
122 PHY_INTERFACE_MODE_RMII,
123 PHY_INTERFACE_MODE_REVRMII,
124 PHY_INTERFACE_MODE_RGMII,
125 PHY_INTERFACE_MODE_RGMII_ID,
126 PHY_INTERFACE_MODE_RGMII_RXID,
127 PHY_INTERFACE_MODE_RGMII_TXID,
128 PHY_INTERFACE_MODE_RTBI,
129 PHY_INTERFACE_MODE_SMII,
130 PHY_INTERFACE_MODE_XGMII,
131 PHY_INTERFACE_MODE_XLGMII,
132 PHY_INTERFACE_MODE_MOCA,
133 PHY_INTERFACE_MODE_PSGMII,
134 PHY_INTERFACE_MODE_QSGMII,
135 PHY_INTERFACE_MODE_TRGMII,
136 PHY_INTERFACE_MODE_100BASEX,
137 PHY_INTERFACE_MODE_1000BASEX,
138 PHY_INTERFACE_MODE_2500BASEX,
139 PHY_INTERFACE_MODE_5GBASER,
140 PHY_INTERFACE_MODE_RXAUI,
141 PHY_INTERFACE_MODE_XAUI,
142 /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */
143 PHY_INTERFACE_MODE_10GBASER,
144 PHY_INTERFACE_MODE_25GBASER,
145 PHY_INTERFACE_MODE_USXGMII,
146 /* 10GBASE-KR - with Clause 73 AN */
147 PHY_INTERFACE_MODE_10GKR,
148 PHY_INTERFACE_MODE_QUSGMII,
149 PHY_INTERFACE_MODE_1000BASEKX,
150 PHY_INTERFACE_MODE_10G_QXGMII,
151 PHY_INTERFACE_MODE_50GBASER,
152 PHY_INTERFACE_MODE_LAUI,
153 PHY_INTERFACE_MODE_100GBASEP,
154 PHY_INTERFACE_MODE_MIILITE,
155 PHY_INTERFACE_MODE_MAX,
156} phy_interface_t;
157
158/* PHY interface mode bitmap handling */
159#define DECLARE_PHY_INTERFACE_MASK(name) \
160 DECLARE_BITMAP(name, PHY_INTERFACE_MODE_MAX)
161
162static inline void phy_interface_zero(unsigned long *intf)
163{
164 bitmap_zero(dst: intf, nbits: PHY_INTERFACE_MODE_MAX);
165}
166
167static inline bool phy_interface_empty(const unsigned long *intf)
168{
169 return bitmap_empty(src: intf, nbits: PHY_INTERFACE_MODE_MAX);
170}
171
172static inline void phy_interface_copy(unsigned long *d, const unsigned long *s)
173{
174 bitmap_copy(dst: d, src: s, nbits: PHY_INTERFACE_MODE_MAX);
175}
176
177static inline unsigned int phy_interface_weight(const unsigned long *intf)
178{
179 return bitmap_weight(src: intf, nbits: PHY_INTERFACE_MODE_MAX);
180}
181
182static inline void phy_interface_and(unsigned long *dst, const unsigned long *a,
183 const unsigned long *b)
184{
185 bitmap_and(dst, src1: a, src2: b, nbits: PHY_INTERFACE_MODE_MAX);
186}
187
188static inline void phy_interface_or(unsigned long *dst, const unsigned long *a,
189 const unsigned long *b)
190{
191 bitmap_or(dst, src1: a, src2: b, nbits: PHY_INTERFACE_MODE_MAX);
192}
193
194static inline void phy_interface_set_rgmii(unsigned long *intf)
195{
196 __set_bit(PHY_INTERFACE_MODE_RGMII, intf);
197 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, intf);
198 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, intf);
199 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, intf);
200}
201
202/**
203 * phy_modes - map phy_interface_t enum to device tree binding of phy-mode
204 * @interface: enum phy_interface_t value
205 *
206 * Description: maps enum &phy_interface_t defined in this file
207 * into the device tree binding of 'phy-mode', so that Ethernet
208 * device driver can get PHY interface from device tree.
209 */
210static inline const char *phy_modes(phy_interface_t interface)
211{
212 switch (interface) {
213 case PHY_INTERFACE_MODE_NA:
214 return "";
215 case PHY_INTERFACE_MODE_INTERNAL:
216 return "internal";
217 case PHY_INTERFACE_MODE_MII:
218 return "mii";
219 case PHY_INTERFACE_MODE_GMII:
220 return "gmii";
221 case PHY_INTERFACE_MODE_SGMII:
222 return "sgmii";
223 case PHY_INTERFACE_MODE_TBI:
224 return "tbi";
225 case PHY_INTERFACE_MODE_REVMII:
226 return "rev-mii";
227 case PHY_INTERFACE_MODE_RMII:
228 return "rmii";
229 case PHY_INTERFACE_MODE_REVRMII:
230 return "rev-rmii";
231 case PHY_INTERFACE_MODE_RGMII:
232 return "rgmii";
233 case PHY_INTERFACE_MODE_RGMII_ID:
234 return "rgmii-id";
235 case PHY_INTERFACE_MODE_RGMII_RXID:
236 return "rgmii-rxid";
237 case PHY_INTERFACE_MODE_RGMII_TXID:
238 return "rgmii-txid";
239 case PHY_INTERFACE_MODE_RTBI:
240 return "rtbi";
241 case PHY_INTERFACE_MODE_SMII:
242 return "smii";
243 case PHY_INTERFACE_MODE_XGMII:
244 return "xgmii";
245 case PHY_INTERFACE_MODE_XLGMII:
246 return "xlgmii";
247 case PHY_INTERFACE_MODE_MOCA:
248 return "moca";
249 case PHY_INTERFACE_MODE_PSGMII:
250 return "psgmii";
251 case PHY_INTERFACE_MODE_QSGMII:
252 return "qsgmii";
253 case PHY_INTERFACE_MODE_TRGMII:
254 return "trgmii";
255 case PHY_INTERFACE_MODE_1000BASEX:
256 return "1000base-x";
257 case PHY_INTERFACE_MODE_1000BASEKX:
258 return "1000base-kx";
259 case PHY_INTERFACE_MODE_2500BASEX:
260 return "2500base-x";
261 case PHY_INTERFACE_MODE_5GBASER:
262 return "5gbase-r";
263 case PHY_INTERFACE_MODE_RXAUI:
264 return "rxaui";
265 case PHY_INTERFACE_MODE_XAUI:
266 return "xaui";
267 case PHY_INTERFACE_MODE_10GBASER:
268 return "10gbase-r";
269 case PHY_INTERFACE_MODE_25GBASER:
270 return "25gbase-r";
271 case PHY_INTERFACE_MODE_USXGMII:
272 return "usxgmii";
273 case PHY_INTERFACE_MODE_10GKR:
274 return "10gbase-kr";
275 case PHY_INTERFACE_MODE_100BASEX:
276 return "100base-x";
277 case PHY_INTERFACE_MODE_QUSGMII:
278 return "qusgmii";
279 case PHY_INTERFACE_MODE_10G_QXGMII:
280 return "10g-qxgmii";
281 case PHY_INTERFACE_MODE_50GBASER:
282 return "50gbase-r";
283 case PHY_INTERFACE_MODE_LAUI:
284 return "laui";
285 case PHY_INTERFACE_MODE_100GBASEP:
286 return "100gbase-p";
287 case PHY_INTERFACE_MODE_MIILITE:
288 return "mii-lite";
289 default:
290 return "unknown";
291 }
292}
293
294/**
295 * rgmii_clock - map link speed to the clock rate
296 * @speed: link speed value
297 *
298 * Description: maps RGMII supported link speeds into the clock rates.
299 * This can also be used for MII, GMII, and RMII interface modes as the
300 * clock rates are identical, but the caller must be aware that errors
301 * for unsupported clock rates will not be signalled.
302 *
303 * Returns: clock rate or negative errno
304 */
305static inline long rgmii_clock(int speed)
306{
307 switch (speed) {
308 case SPEED_10:
309 return 2500000;
310 case SPEED_100:
311 return 25000000;
312 case SPEED_1000:
313 return 125000000;
314 default:
315 return -EINVAL;
316 }
317}
318
319#define PHY_MAX_ADDR 32
320
321/* Used when trying to connect to a specific phy (mii bus id:phy device id) */
322#define PHY_ID_FMT "%s:%02x"
323#define PHY_ID_SIZE (MII_BUS_ID_SIZE + 3)
324
325#define MII_BUS_ID_SIZE 61
326
327struct device;
328struct kernel_hwtstamp_config;
329struct phylink;
330struct sfp_bus;
331struct sfp_upstream_ops;
332struct sk_buff;
333
334/**
335 * struct mdio_bus_stats - Statistics counters for MDIO busses
336 * @transfers: Total number of transfers, i.e. @writes + @reads
337 * @errors: Number of MDIO transfers that returned an error
338 * @writes: Number of write transfers
339 * @reads: Number of read transfers
340 * @syncp: Synchronisation for incrementing statistics
341 */
342struct mdio_bus_stats {
343 u64_stats_t transfers;
344 u64_stats_t errors;
345 u64_stats_t writes;
346 u64_stats_t reads;
347 /* Must be last, add new statistics above */
348 struct u64_stats_sync syncp;
349};
350
351/**
352 * struct mii_bus - Represents an MDIO bus
353 *
354 * @owner: Who owns this device
355 * @name: User friendly name for this MDIO device, or driver name
356 * @id: Unique identifier for this bus, typical from bus hierarchy
357 * @priv: Driver private data
358 *
359 * The Bus class for PHYs. Devices which provide access to
360 * PHYs should register using this structure
361 */
362struct mii_bus {
363 struct module *owner;
364 const char *name;
365 char id[MII_BUS_ID_SIZE];
366 void *priv;
367 /** @read: Perform a read transfer on the bus */
368 int (*read)(struct mii_bus *bus, int addr, int regnum);
369 /** @write: Perform a write transfer on the bus */
370 int (*write)(struct mii_bus *bus, int addr, int regnum, u16 val);
371 /** @read_c45: Perform a C45 read transfer on the bus */
372 int (*read_c45)(struct mii_bus *bus, int addr, int devnum, int regnum);
373 /** @write_c45: Perform a C45 write transfer on the bus */
374 int (*write_c45)(struct mii_bus *bus, int addr, int devnum,
375 int regnum, u16 val);
376 /** @reset: Perform a reset of the bus */
377 int (*reset)(struct mii_bus *bus);
378
379 /** @stats: Statistic counters per device on the bus */
380 struct mdio_bus_stats stats[PHY_MAX_ADDR];
381
382 /**
383 * @mdio_lock: A lock to ensure that only one thing can read/write
384 * the MDIO bus at a time
385 */
386 struct mutex mdio_lock;
387
388 /** @parent: Parent device of this bus */
389 struct device *parent;
390 /** @state: State of bus structure */
391 enum {
392 MDIOBUS_ALLOCATED = 1,
393 MDIOBUS_REGISTERED,
394 MDIOBUS_UNREGISTERED,
395 MDIOBUS_RELEASED,
396 } state;
397
398 /** @dev: Kernel device representation */
399 struct device dev;
400
401 /** @mdio_map: list of all MDIO devices on bus */
402 struct mdio_device *mdio_map[PHY_MAX_ADDR];
403
404 /** @phy_mask: PHY addresses to be ignored when probing */
405 u32 phy_mask;
406
407 /** @phy_ignore_ta_mask: PHY addresses to ignore the TA/read failure */
408 u32 phy_ignore_ta_mask;
409
410 /**
411 * @irq: An array of interrupts, each PHY's interrupt at the index
412 * matching its address
413 */
414 int irq[PHY_MAX_ADDR];
415
416 /** @reset_delay_us: GPIO reset pulse width in microseconds */
417 int reset_delay_us;
418 /** @reset_post_delay_us: GPIO reset deassert delay in microseconds */
419 int reset_post_delay_us;
420 /** @reset_gpiod: Reset GPIO descriptor pointer */
421 struct gpio_desc *reset_gpiod;
422
423 /** @shared_lock: protect access to the shared element */
424 struct mutex shared_lock;
425
426#if IS_ENABLED(CONFIG_PHY_PACKAGE)
427 /** @shared: shared state across different PHYs */
428 struct phy_package_shared *shared[PHY_MAX_ADDR];
429#endif
430};
431#define to_mii_bus(d) container_of(d, struct mii_bus, dev)
432
433struct mii_bus *mdiobus_alloc_size(size_t size);
434
435/**
436 * mdiobus_alloc - Allocate an MDIO bus structure
437 *
438 * The internal state of the MDIO bus will be set of MDIOBUS_ALLOCATED ready
439 * for the driver to register the bus.
440 */
441static inline struct mii_bus *mdiobus_alloc(void)
442{
443 return mdiobus_alloc_size(size: 0);
444}
445
446int __mdiobus_register(struct mii_bus *bus, struct module *owner);
447int __devm_mdiobus_register(struct device *dev, struct mii_bus *bus,
448 struct module *owner);
449#define mdiobus_register(bus) __mdiobus_register(bus, THIS_MODULE)
450#define devm_mdiobus_register(dev, bus) \
451 __devm_mdiobus_register(dev, bus, THIS_MODULE)
452
453void mdiobus_unregister(struct mii_bus *bus);
454void mdiobus_free(struct mii_bus *bus);
455struct mii_bus *devm_mdiobus_alloc_size(struct device *dev, int sizeof_priv);
456static inline struct mii_bus *devm_mdiobus_alloc(struct device *dev)
457{
458 return devm_mdiobus_alloc_size(dev, sizeof_priv: 0);
459}
460
461struct mii_bus *mdio_find_bus(const char *mdio_name);
462struct phy_device *mdiobus_scan_c22(struct mii_bus *bus, int addr);
463
464#define PHY_INTERRUPT_DISABLED false
465#define PHY_INTERRUPT_ENABLED true
466
467/**
468 * enum phy_state - PHY state machine states:
469 *
470 * @PHY_DOWN: PHY device and driver are not ready for anything. probe
471 * should be called if and only if the PHY is in this state,
472 * given that the PHY device exists.
473 * - PHY driver probe function will set the state to @PHY_READY
474 *
475 * @PHY_READY: PHY is ready to send and receive packets, but the
476 * controller is not. By default, PHYs which do not implement
477 * probe will be set to this state by phy_probe().
478 * - start will set the state to UP
479 *
480 * @PHY_UP: The PHY and attached device are ready to do work.
481 * Interrupts should be started here.
482 * - timer moves to @PHY_NOLINK or @PHY_RUNNING
483 *
484 * @PHY_NOLINK: PHY is up, but not currently plugged in.
485 * - irq or timer will set @PHY_RUNNING if link comes back
486 * - phy_stop moves to @PHY_HALTED
487 *
488 * @PHY_RUNNING: PHY is currently up, running, and possibly sending
489 * and/or receiving packets
490 * - irq or timer will set @PHY_NOLINK if link goes down
491 * - phy_stop moves to @PHY_HALTED
492 *
493 * @PHY_CABLETEST: PHY is performing a cable test. Packet reception/sending
494 * is not expected to work, carrier will be indicated as down. PHY will be
495 * poll once per second, or on interrupt for it current state.
496 * Once complete, move to UP to restart the PHY.
497 * - phy_stop aborts the running test and moves to @PHY_HALTED
498 *
499 * @PHY_HALTED: PHY is up, but no polling or interrupts are done.
500 * - phy_start moves to @PHY_UP
501 *
502 * @PHY_ERROR: PHY is up, but is in an error state.
503 * - phy_stop moves to @PHY_HALTED
504 */
505enum phy_state {
506 PHY_DOWN = 0,
507 PHY_READY,
508 PHY_HALTED,
509 PHY_ERROR,
510 PHY_UP,
511 PHY_RUNNING,
512 PHY_NOLINK,
513 PHY_CABLETEST,
514};
515
516#define MDIO_MMD_NUM 32
517
518/**
519 * struct phy_c45_device_ids - 802.3-c45 Device Identifiers
520 * @devices_in_package: IEEE 802.3 devices in package register value.
521 * @mmds_present: bit vector of MMDs present.
522 * @device_ids: The device identifier for each present device.
523 */
524struct phy_c45_device_ids {
525 u32 devices_in_package;
526 u32 mmds_present;
527 u32 device_ids[MDIO_MMD_NUM];
528};
529
530struct macsec_context;
531struct macsec_ops;
532
533/**
534 * struct phy_oatc14_sqi_capability - SQI capability information for OATC14
535 * 10Base-T1S PHY
536 * @updated: Indicates whether the SQI capability fields have been updated.
537 * @sqi_max: Maximum supported Signal Quality Indicator (SQI) level reported by
538 * the PHY.
539 * @sqiplus_bits: Bits for SQI+ levels supported by the PHY.
540 * 0 - SQI+ is not supported
541 * 3 - SQI+ is supported, using 3 bits (8 levels)
542 * 4 - SQI+ is supported, using 4 bits (16 levels)
543 * 5 - SQI+ is supported, using 5 bits (32 levels)
544 * 6 - SQI+ is supported, using 6 bits (64 levels)
545 * 7 - SQI+ is supported, using 7 bits (128 levels)
546 * 8 - SQI+ is supported, using 8 bits (256 levels)
547 *
548 * This structure is used by the OATC14 10Base-T1S PHY driver to store the SQI
549 * and SQI+ capability information retrieved from the PHY.
550 */
551struct phy_oatc14_sqi_capability {
552 bool updated;
553 int sqi_max;
554 u8 sqiplus_bits;
555};
556
557/**
558 * struct phy_device - An instance of a PHY
559 *
560 * @mdio: MDIO bus this PHY is on
561 * @drv: Pointer to the driver for this PHY instance
562 * @devlink: Create a link between phy dev and mac dev, if the external phy
563 * used by current mac interface is managed by another mac interface.
564 * @phyindex: Unique id across the phy's parent tree of phys to address the PHY
565 * from userspace, similar to ifindex. A zero index means the PHY
566 * wasn't assigned an id yet.
567 * @phy_id: UID for this device found during discovery
568 * @c45_ids: 802.3-c45 Device Identifiers if is_c45.
569 * @is_c45: Set to true if this PHY uses clause 45 addressing.
570 * @is_internal: Set to true if this PHY is internal to a MAC.
571 * @is_pseudo_fixed_link: Set to true if this PHY is an Ethernet switch, etc.
572 * @is_gigabit_capable: Set to true if PHY supports 1000Mbps
573 * @has_fixups: Set to true if this PHY has fixups/quirks.
574 * @suspended: Set to true if this PHY has been suspended successfully.
575 * @suspended_by_mdio_bus: Set to true if this PHY was suspended by MDIO bus.
576 * @sysfs_links: Internal boolean tracking sysfs symbolic links setup/removal.
577 * @loopback_enabled: Set true if this PHY has been loopbacked successfully.
578 * @downshifted_rate: Set true if link speed has been downshifted.
579 * @is_on_sfp_module: Set true if PHY is located on an SFP module.
580 * @mac_managed_pm: Set true if MAC driver takes of suspending/resuming PHY
581 * @wol_enabled: Set to true if the PHY or the attached MAC have Wake-on-LAN
582 * enabled.
583 * @is_genphy_driven: PHY is driven by one of the generic PHY drivers
584 * @state: State of the PHY for management purposes
585 * @dev_flags: Device-specific flags used by the PHY driver.
586 *
587 * - Bits [15:0] are free to use by the PHY driver to communicate
588 * driver specific behavior.
589 * - Bits [23:16] are currently reserved for future use.
590 * - Bits [31:24] are reserved for defining generic
591 * PHY driver behavior.
592 * @irq: IRQ number of the PHY's interrupt (-1 if none)
593 * @phylink: Pointer to phylink instance for this PHY
594 * @sfp_bus_attached: Flag indicating whether the SFP bus has been attached
595 * @sfp_bus: SFP bus attached to this PHY's fiber port
596 * @attached_dev: The attached enet driver's device instance ptr
597 * @adjust_link: Callback for the enet controller to respond to changes: in the
598 * link state.
599 * @phy_link_change: Callback for phylink for notification of link change
600 * @macsec_ops: MACsec offloading ops.
601 *
602 * @speed: Current link speed
603 * @duplex: Current duplex
604 * @port: Current port
605 * @pause: Current pause
606 * @asym_pause: Current asymmetric pause
607 * @supported: Combined MAC/PHY supported linkmodes
608 * @advertising: Currently advertised linkmodes
609 * @adv_old: Saved advertised while power saving for WoL
610 * @supported_eee: supported PHY EEE linkmodes
611 * @advertising_eee: Currently advertised EEE linkmodes
612 * @enable_tx_lpi: When True, MAC should transmit LPI to PHY
613 * @eee_active: phylib private state, indicating that EEE has been negotiated
614 * @eee_cfg: User configuration of EEE
615 * @lp_advertising: Current link partner advertised linkmodes
616 * @host_interfaces: PHY interface modes supported by host
617 * @eee_disabled_modes: Energy efficient ethernet modes not to be advertised
618 * @autoneg: Flag autoneg being used
619 * @rate_matching: Current rate matching mode
620 * @link: Current link state
621 * @autoneg_complete: Flag auto negotiation of the link has completed
622 * @mdix: Current crossover
623 * @mdix_ctrl: User setting of crossover
624 * @pma_extable: Cached value of PMA/PMD Extended Abilities Register
625 * @interrupts: Flag interrupts have been enabled
626 * @irq_suspended: Flag indicating PHY is suspended and therefore interrupt
627 * handling shall be postponed until PHY has resumed
628 * @irq_rerun: Flag indicating interrupts occurred while PHY was suspended,
629 * requiring a rerun of the interrupt handler after resume
630 * @default_timestamp: Flag indicating whether we are using the phy
631 * timestamp as the default one
632 * @interface: enum phy_interface_t value
633 * @possible_interfaces: bitmap if interface modes that the attached PHY
634 * will switch between depending on media speed.
635 * @skb: Netlink message for cable diagnostics
636 * @nest: Netlink nest used for cable diagnostics
637 * @ehdr: nNtlink header for cable diagnostics
638 * @phy_led_triggers: Array of LED triggers
639 * @phy_num_led_triggers: Number of triggers in @phy_led_triggers
640 * @led_link_trigger: LED trigger for link up/down
641 * @last_triggered: last LED trigger for link speed
642 * @leds: list of PHY LED structures
643 * @master_slave_set: User requested master/slave configuration
644 * @master_slave_get: Current master/slave advertisement
645 * @master_slave_state: Current master/slave configuration
646 * @mii_ts: Pointer to time stamper callbacks
647 * @psec: Pointer to Power Sourcing Equipment control struct
648 * @lock: Mutex for serialization access to PHY
649 * @state_queue: Work queue for state machine
650 * @link_down_events: Number of times link was lost
651 * @shared: Pointer to private data shared by phys in one package
652 * @priv: Pointer to driver private data
653 * @oatc14_sqi_capability: SQI capability information for OATC14 10Base-T1S PHY
654 *
655 * interrupts currently only supports enabled or disabled,
656 * but could be changed in the future to support enabling
657 * and disabling specific interrupts
658 *
659 * Contains some infrastructure for polling and interrupt
660 * handling, as well as handling shifts in PHY hardware state
661 */
662struct phy_device {
663 struct mdio_device mdio;
664
665 /* Information about the PHY type */
666 /* And management functions */
667 const struct phy_driver *drv;
668
669 struct device_link *devlink;
670
671 u32 phyindex;
672 u32 phy_id;
673
674 struct phy_c45_device_ids c45_ids;
675 unsigned is_c45:1;
676 unsigned is_internal:1;
677 unsigned is_pseudo_fixed_link:1;
678 unsigned is_gigabit_capable:1;
679 unsigned has_fixups:1;
680 unsigned suspended:1;
681 unsigned suspended_by_mdio_bus:1;
682 unsigned sysfs_links:1;
683 unsigned loopback_enabled:1;
684 unsigned downshifted_rate:1;
685 unsigned is_on_sfp_module:1;
686 unsigned mac_managed_pm:1;
687 unsigned wol_enabled:1;
688 unsigned is_genphy_driven:1;
689
690 unsigned autoneg:1;
691 /* The most recently read link state */
692 unsigned link:1;
693 unsigned autoneg_complete:1;
694 bool pause:1;
695 bool asym_pause:1;
696
697 /* Interrupts are enabled */
698 unsigned interrupts:1;
699 unsigned irq_suspended:1;
700 unsigned irq_rerun:1;
701
702 unsigned default_timestamp:1;
703
704 int rate_matching;
705
706 enum phy_state state;
707
708 u32 dev_flags;
709
710 phy_interface_t interface;
711 DECLARE_PHY_INTERFACE_MASK(possible_interfaces);
712
713 /*
714 * forced speed & duplex (no autoneg)
715 * partner speed & duplex & pause (autoneg)
716 */
717 int speed;
718 int duplex;
719 int port;
720 u8 master_slave_get;
721 u8 master_slave_set;
722 u8 master_slave_state;
723
724 /* Union of PHY and Attached devices' supported link modes */
725 /* See ethtool.h for more info */
726 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
727 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
728 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising);
729 /* used with phy_speed_down */
730 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv_old);
731 /* used for eee validation and configuration*/
732 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported_eee);
733 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising_eee);
734 /* Energy efficient ethernet modes which should be prohibited */
735 __ETHTOOL_DECLARE_LINK_MODE_MASK(eee_disabled_modes);
736 bool enable_tx_lpi;
737 bool eee_active;
738 struct eee_config eee_cfg;
739
740 /* Host supported PHY interface types. Should be ignored if empty. */
741 DECLARE_PHY_INTERFACE_MASK(host_interfaces);
742
743#ifdef CONFIG_LED_TRIGGER_PHY
744 struct phy_led_trigger *phy_led_triggers;
745 unsigned int phy_num_led_triggers;
746 struct phy_led_trigger *last_triggered;
747
748 struct phy_led_trigger *led_link_trigger;
749#endif
750 struct list_head leds;
751
752 /*
753 * Interrupt number for this PHY
754 * -1 means no interrupt
755 */
756 int irq;
757
758 /* private data pointer */
759 /* For use by PHYs to maintain extra state */
760 void *priv;
761
762#if IS_ENABLED(CONFIG_PHY_PACKAGE)
763 /* shared data pointer */
764 /* For use by PHYs inside the same package that need a shared state. */
765 struct phy_package_shared *shared;
766#endif
767
768 /* Reporting cable test results */
769 struct sk_buff *skb;
770 void *ehdr;
771 struct nlattr *nest;
772
773 /* Interrupt and Polling infrastructure */
774 struct delayed_work state_queue;
775
776 struct mutex lock;
777
778 /* This may be modified under the rtnl lock */
779 bool sfp_bus_attached;
780 struct sfp_bus *sfp_bus;
781 struct phylink *phylink;
782 struct net_device *attached_dev;
783 struct mii_timestamper *mii_ts;
784 struct pse_control *psec;
785
786 u8 mdix;
787 u8 mdix_ctrl;
788
789 int pma_extable;
790
791 unsigned int link_down_events;
792
793 void (*phy_link_change)(struct phy_device *phydev, bool up);
794 void (*adjust_link)(struct net_device *dev);
795
796#if IS_ENABLED(CONFIG_MACSEC)
797 /* MACsec management functions */
798 const struct macsec_ops *macsec_ops;
799#endif
800
801 struct phy_oatc14_sqi_capability oatc14_sqi_capability;
802};
803
804/* Generic phy_device::dev_flags */
805#define PHY_F_NO_IRQ 0x80000000
806#define PHY_F_RXC_ALWAYS_ON 0x40000000
807
808#define to_phy_device(__dev) container_of_const(to_mdio_device(__dev), struct phy_device, mdio)
809
810/**
811 * struct phy_tdr_config - Configuration of a TDR raw test
812 *
813 * @first: Distance for first data collection point
814 * @last: Distance for last data collection point
815 * @step: Step between data collection points
816 * @pair: Bitmap of cable pairs to collect data for
817 *
818 * A structure containing possible configuration parameters
819 * for a TDR cable test. The driver does not need to implement
820 * all the parameters, but should report what is actually used.
821 * All distances are in centimeters.
822 */
823struct phy_tdr_config {
824 u32 first;
825 u32 last;
826 u32 step;
827 s8 pair;
828};
829#define PHY_PAIR_ALL -1
830
831/**
832 * enum link_inband_signalling - in-band signalling modes that are supported
833 *
834 * @LINK_INBAND_DISABLE: in-band signalling can be disabled
835 * @LINK_INBAND_ENABLE: in-band signalling can be enabled without bypass
836 * @LINK_INBAND_BYPASS: in-band signalling can be enabled with bypass
837 *
838 * The possible and required bits can only be used if the valid bit is set.
839 * If possible is clear, that means inband signalling can not be used.
840 * Required is only valid when possible is set, and means that inband
841 * signalling must be used.
842 */
843enum link_inband_signalling {
844 LINK_INBAND_DISABLE = BIT(0),
845 LINK_INBAND_ENABLE = BIT(1),
846 LINK_INBAND_BYPASS = BIT(2),
847};
848
849/**
850 * struct phy_plca_cfg - Configuration of the PLCA (Physical Layer Collision
851 * Avoidance) Reconciliation Sublayer.
852 *
853 * @version: read-only PLCA register map version. -1 = not available. Ignored
854 * when setting the configuration. Format is the same as reported by the PLCA
855 * IDVER register (31.CA00). -1 = not available.
856 * @enabled: PLCA configured mode (enabled/disabled). -1 = not available / don't
857 * set. 0 = disabled, anything else = enabled.
858 * @node_id: the PLCA local node identifier. -1 = not available / don't set.
859 * Allowed values [0 .. 254]. 255 = node disabled.
860 * @node_cnt: the PLCA node count (maximum number of nodes having a TO). Only
861 * meaningful for the coordinator (node_id = 0). -1 = not available / don't
862 * set. Allowed values [1 .. 255].
863 * @to_tmr: The value of the PLCA to_timer in bit-times, which determines the
864 * PLCA transmit opportunity window opening. See IEEE802.3 Clause 148 for
865 * more details. The to_timer shall be set equal over all nodes.
866 * -1 = not available / don't set. Allowed values [0 .. 255].
867 * @burst_cnt: controls how many additional frames a node is allowed to send in
868 * single transmit opportunity (TO). The default value of 0 means that the
869 * node is allowed exactly one frame per TO. A value of 1 allows two frames
870 * per TO, and so on. -1 = not available / don't set.
871 * Allowed values [0 .. 255].
872 * @burst_tmr: controls how many bit times to wait for the MAC to send a new
873 * frame before interrupting the burst. This value should be set to a value
874 * greater than the MAC inter-packet gap (which is typically 96 bits).
875 * -1 = not available / don't set. Allowed values [0 .. 255].
876 *
877 * A structure containing configuration parameters for setting/getting the PLCA
878 * RS configuration. The driver does not need to implement all the parameters,
879 * but should report what is actually used.
880 */
881struct phy_plca_cfg {
882 int version;
883 int enabled;
884 int node_id;
885 int node_cnt;
886 int to_tmr;
887 int burst_cnt;
888 int burst_tmr;
889};
890
891/**
892 * struct phy_plca_status - Status of the PLCA (Physical Layer Collision
893 * Avoidance) Reconciliation Sublayer.
894 *
895 * @pst: The PLCA status as reported by the PST bit in the PLCA STATUS
896 * register(31.CA03), indicating BEACON activity.
897 *
898 * A structure containing status information of the PLCA RS configuration.
899 * The driver does not need to implement all the parameters, but should report
900 * what is actually used.
901 */
902struct phy_plca_status {
903 bool pst;
904};
905
906/* Modes for PHY LED configuration */
907enum phy_led_modes {
908 PHY_LED_ACTIVE_HIGH = 0,
909 PHY_LED_ACTIVE_LOW = 1,
910 PHY_LED_INACTIVE_HIGH_IMPEDANCE = 2,
911
912 /* keep it last */
913 __PHY_LED_MODES_NUM,
914};
915
916/**
917 * struct phy_led: An LED driven by the PHY
918 *
919 * @list: List of LEDs
920 * @phydev: PHY this LED is attached to
921 * @led_cdev: Standard LED class structure
922 * @index: Number of the LED
923 */
924struct phy_led {
925 struct list_head list;
926 struct phy_device *phydev;
927 struct led_classdev led_cdev;
928 u8 index;
929};
930
931#define to_phy_led(d) container_of(d, struct phy_led, led_cdev)
932
933/*
934 * PHY_MSE_CAP_* - Bitmask flags for Mean Square Error (MSE) capabilities
935 *
936 * These flags describe which MSE metrics and selectors are implemented
937 * by the PHY for the current link mode. They are used in
938 * struct phy_mse_capability.supported_caps.
939 *
940 * Standardization:
941 * The OPEN Alliance (OA) defines the presence of MSE/SQI/pMSE but not their
942 * numeric scaling, update intervals, or aggregation windows. See:
943 * OA 100BASE-T1 TC1 v1.0, sections 6.1.1-6.1.3
944 * OA 1000BASE-T1 TC12 v2.2, sections 6.1.1-6.1.2
945 *
946 * Description of flags:
947 *
948 * PHY_MSE_CAP_CHANNEL_A
949 * Per-pair diagnostics for Channel A are supported. Mapping to the
950 * physical wire pair may depend on MDI/MDI-X polarity.
951 *
952 * PHY_MSE_CAP_CHANNEL_B, _C, _D
953 * Same as above for channels B-D.
954 *
955 * PHY_MSE_CAP_WORST_CHANNEL
956 * The PHY or driver can identify and report the single worst-performing
957 * channel without querying each one individually.
958 *
959 * PHY_MSE_CAP_LINK
960 * The PHY provides only a link-wide aggregate measurement or cannot map
961 * results to a specific pair (for example 100BASE-TX with unknown
962 * MDI/MDI-X).
963 *
964 * PHY_MSE_CAP_AVG
965 * Average MSE (mean DCQ metric) is supported. For 100/1000BASE-T1 the OA
966 * recommends 2^16 symbols, scaled 0..511, but the exact scaling is
967 * vendor-specific.
968 *
969 * PHY_MSE_CAP_PEAK
970 * Peak MSE (current peak within the measurement window) is supported.
971 * Defined as pMSE for 100BASE-T1; vendor-specific for others.
972 *
973 * PHY_MSE_CAP_WORST_PEAK
974 * Latched worst-case peak MSE since the last read (read-to-clear if
975 * implemented). Optional in OA 100BASE-T1 TC1 6.1.3.
976 */
977#define PHY_MSE_CAP_CHANNEL_A BIT(0)
978#define PHY_MSE_CAP_CHANNEL_B BIT(1)
979#define PHY_MSE_CAP_CHANNEL_C BIT(2)
980#define PHY_MSE_CAP_CHANNEL_D BIT(3)
981#define PHY_MSE_CAP_WORST_CHANNEL BIT(4)
982#define PHY_MSE_CAP_LINK BIT(5)
983#define PHY_MSE_CAP_AVG BIT(6)
984#define PHY_MSE_CAP_PEAK BIT(7)
985#define PHY_MSE_CAP_WORST_PEAK BIT(8)
986
987/*
988 * enum phy_mse_channel - Identifiers for selecting MSE measurement channels
989 *
990 * PHY_MSE_CHANNEL_A - PHY_MSE_CHANNEL_D
991 * Select per-pair measurement for the corresponding channel.
992 *
993 * PHY_MSE_CHANNEL_WORST
994 * Select the single worst-performing channel reported by hardware.
995 *
996 * PHY_MSE_CHANNEL_LINK
997 * Select link-wide aggregate data (used when per-pair results are
998 * unavailable).
999 */
1000enum phy_mse_channel {
1001 PHY_MSE_CHANNEL_A,
1002 PHY_MSE_CHANNEL_B,
1003 PHY_MSE_CHANNEL_C,
1004 PHY_MSE_CHANNEL_D,
1005 PHY_MSE_CHANNEL_WORST,
1006 PHY_MSE_CHANNEL_LINK,
1007};
1008
1009/**
1010 * struct phy_mse_capability - Capabilities of Mean Square Error (MSE)
1011 * measurement interface
1012 *
1013 * Standardization notes:
1014 *
1015 * - Presence of MSE/SQI/pMSE is defined by OPEN Alliance specs, but numeric
1016 * scaling, refresh/update rate and aggregation windows are not fixed and
1017 * are vendor-/product-specific. (OA 100BASE-T1 TC1 v1.0 6.1.*;
1018 * OA 1000BASE-T1 TC12 v2.2 6.1.*)
1019 *
1020 * - Typical recommendations: 2^16 symbols and 0..511 scaling for MSE; pMSE only
1021 * defined for 100BASE-T1 (sliding window example), others are vendor
1022 * extensions. Drivers must report actual scale/limits here.
1023 *
1024 * Describes the MSE measurement capabilities for the current link mode. These
1025 * properties are dynamic and may change when link settings are modified.
1026 * Callers should re-query this capability after any link state change to
1027 * ensure they have the most up-to-date information.
1028 *
1029 * Callers should only request measurements for channels and types that are
1030 * indicated as supported by the @supported_caps bitmask. If @supported_caps
1031 * is 0, the device provides no MSE diagnostics, and driver operations should
1032 * typically return -EOPNOTSUPP.
1033 *
1034 * Snapshot values for average and peak MSE can be normalized to a 0..1 ratio
1035 * by dividing the raw snapshot by the corresponding @max_average_mse or
1036 * @max_peak_mse value.
1037 *
1038 * @max_average_mse: The maximum value for an average MSE snapshot. This
1039 * defines the scale for the measurement. If the PHY_MSE_CAP_AVG capability is
1040 * supported, this value MUST be greater than 0. (vendor-specific units).
1041 * @max_peak_mse: The maximum value for a peak MSE snapshot. If either
1042 * PHY_MSE_CAP_PEAK or PHY_MSE_CAP_WORST_PEAK is supported, this value MUST
1043 * be greater than 0. (vendor-specific units).
1044 * @refresh_rate_ps: The typical interval, in picoseconds, between hardware
1045 * updates of the MSE values. This is an estimate, and callers should not
1046 * assume synchronous sampling. (vendor-specific units).
1047 * @num_symbols: The number of symbols aggregated per hardware sample to
1048 * calculate the MSE. (vendor-specific units).
1049 * @supported_caps: A bitmask of PHY_MSE_CAP_* values indicating which
1050 * measurement types (e.g., average, peak) and channels
1051 * (e.g., per-pair or link-wide) are supported.
1052 */
1053struct phy_mse_capability {
1054 u64 max_average_mse;
1055 u64 max_peak_mse;
1056 u64 refresh_rate_ps;
1057 u64 num_symbols;
1058 u32 supported_caps;
1059};
1060
1061/**
1062 * struct phy_mse_snapshot - A snapshot of Mean Square Error (MSE) diagnostics
1063 *
1064 * Holds a set of MSE diagnostic values that were all captured from a single
1065 * measurement window.
1066 *
1067 * Values are raw, device-scaled and not normalized. Use struct
1068 * phy_mse_capability to interpret the scale and sampling window.
1069 *
1070 * @average_mse: The average MSE value over the measurement window.
1071 * OPEN Alliance references MSE as a DCQ metric; recommends 2^16 symbols and
1072 * 0..511 scaling. Exact scale and refresh are vendor-specific.
1073 * (100BASE-T1 TC1 v1.0 6.1.1; 1000BASE-T1 TC12 v2.2 6.1.1).
1074 *
1075 * @peak_mse: The peak MSE value observed within the measurement window.
1076 * For 100BASE-T1, "pMSE" is optional and may be implemented via a sliding
1077 * 128-symbol window with periodic capture; not standardized for 1000BASE-T1.
1078 * (100BASE-T1 TC1 v1.0 6.1.3, Table "DCQ.peakMSE").
1079 *
1080 * @worst_peak_mse: A latched high-water mark of the peak MSE since last read
1081 * (read-to-clear if implemented). OPEN Alliance shows a latched "worst case
1082 * peak MSE" for 100BASE-T1 pMSE; availability/semantics outside that are
1083 * vendor-specific. (100BASE-T1 TC1 v1.0 6.1.3, DCQ.peakMSE high byte;
1084 * 1000BASE-T1 TC12 v2.2 treats DCQ details as vendor-specific.)
1085 */
1086struct phy_mse_snapshot {
1087 u64 average_mse;
1088 u64 peak_mse;
1089 u64 worst_peak_mse;
1090};
1091
1092/**
1093 * struct phy_driver - Driver structure for a particular PHY type
1094 *
1095 * @mdiodrv: Data common to all MDIO devices
1096 * @phy_id: The result of reading the UID registers of this PHY
1097 * type, and ANDing them with the phy_id_mask. This driver
1098 * only works for PHYs with IDs which match this field
1099 * @name: The friendly name of this PHY type
1100 * @phy_id_mask: Defines the important bits of the phy_id
1101 * @features: A mandatory list of features (speed, duplex, etc)
1102 * supported by this PHY
1103 * @flags: A bitfield defining certain other features this PHY
1104 * supports (like interrupts)
1105 * @driver_data: Static driver data
1106 *
1107 * All functions are optional. If config_aneg or read_status
1108 * are not implemented, the phy core uses the genphy versions.
1109 * Note that none of these functions should be called from
1110 * interrupt time. The goal is for the bus read/write functions
1111 * to be able to block when the bus transaction is happening,
1112 * and be freed up by an interrupt (The MPC85xx has this ability,
1113 * though it is not currently supported in the driver).
1114 */
1115struct phy_driver {
1116 struct mdio_driver_common mdiodrv;
1117 u32 phy_id;
1118 char *name;
1119 u32 phy_id_mask;
1120 const unsigned long * const features;
1121 u32 flags;
1122 const void *driver_data;
1123
1124 /**
1125 * @soft_reset: Called to issue a PHY software reset
1126 */
1127 int (*soft_reset)(struct phy_device *phydev);
1128
1129 /**
1130 * @config_init: Called to initialize the PHY,
1131 * including after a reset
1132 */
1133 int (*config_init)(struct phy_device *phydev);
1134
1135 /**
1136 * @probe: Called during discovery. Used to set
1137 * up device-specific structures, if any
1138 */
1139 int (*probe)(struct phy_device *phydev);
1140
1141 /**
1142 * @get_features: Probe the hardware to determine what
1143 * abilities it has. Should only set phydev->supported.
1144 */
1145 int (*get_features)(struct phy_device *phydev);
1146
1147 /**
1148 * @inband_caps: query whether in-band is supported for the given PHY
1149 * interface mode. Returns a bitmask of bits defined by enum
1150 * link_inband_signalling.
1151 */
1152 unsigned int (*inband_caps)(struct phy_device *phydev,
1153 phy_interface_t interface);
1154
1155 /**
1156 * @config_inband: configure in-band mode for the PHY
1157 */
1158 int (*config_inband)(struct phy_device *phydev, unsigned int modes);
1159
1160 /**
1161 * @get_rate_matching: Get the supported type of rate matching for a
1162 * particular phy interface. This is used by phy consumers to determine
1163 * whether to advertise lower-speed modes for that interface. It is
1164 * assumed that if a rate matching mode is supported on an interface,
1165 * then that interface's rate can be adapted to all slower link speeds
1166 * supported by the phy. If the interface is not supported, this should
1167 * return %RATE_MATCH_NONE.
1168 */
1169 int (*get_rate_matching)(struct phy_device *phydev,
1170 phy_interface_t iface);
1171
1172 /* PHY Power Management */
1173 /** @suspend: Suspend the hardware, saving state if needed */
1174 int (*suspend)(struct phy_device *phydev);
1175 /** @resume: Resume the hardware, restoring state if needed */
1176 int (*resume)(struct phy_device *phydev);
1177
1178 /**
1179 * @config_aneg: Configures the advertisement and resets
1180 * autonegotiation if phydev->autoneg is on,
1181 * forces the speed to the current settings in phydev
1182 * if phydev->autoneg is off
1183 */
1184 int (*config_aneg)(struct phy_device *phydev);
1185
1186 /** @aneg_done: Determines the auto negotiation result */
1187 int (*aneg_done)(struct phy_device *phydev);
1188
1189 /** @read_status: Determines the negotiated speed and duplex */
1190 int (*read_status)(struct phy_device *phydev);
1191
1192 /**
1193 * @config_intr: Enables or disables interrupts.
1194 * It should also clear any pending interrupts prior to enabling the
1195 * IRQs and after disabling them.
1196 */
1197 int (*config_intr)(struct phy_device *phydev);
1198
1199 /** @handle_interrupt: Override default interrupt handling */
1200 irqreturn_t (*handle_interrupt)(struct phy_device *phydev);
1201
1202 /** @remove: Clears up any memory if needed */
1203 void (*remove)(struct phy_device *phydev);
1204
1205 /**
1206 * @match_phy_device: Returns true if this is a suitable
1207 * driver for the given phydev. If NULL, matching is based on
1208 * phy_id and phy_id_mask.
1209 */
1210 int (*match_phy_device)(struct phy_device *phydev,
1211 const struct phy_driver *phydrv);
1212
1213 /**
1214 * @set_wol: Some devices (e.g. qnap TS-119P II) require PHY
1215 * register changes to enable Wake on LAN, so set_wol is
1216 * provided to be called in the ethernet driver's set_wol
1217 * function.
1218 */
1219 int (*set_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol);
1220
1221 /**
1222 * @get_wol: See set_wol, but for checking whether Wake on LAN
1223 * is enabled.
1224 */
1225 void (*get_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol);
1226
1227 /**
1228 * @link_change_notify: Called to inform a PHY device driver
1229 * when the core is about to change the link state. This
1230 * callback is supposed to be used as fixup hook for drivers
1231 * that need to take action when the link state
1232 * changes. Drivers are by no means allowed to mess with the
1233 * PHY device structure in their implementations.
1234 */
1235 void (*link_change_notify)(struct phy_device *dev);
1236
1237 /**
1238 * @read_mmd: PHY specific driver override for reading a MMD
1239 * register. This function is optional for PHY specific
1240 * drivers. When not provided, the default MMD read function
1241 * will be used by phy_read_mmd(), which will use either a
1242 * direct read for Clause 45 PHYs or an indirect read for
1243 * Clause 22 PHYs. devnum is the MMD device number within the
1244 * PHY device, regnum is the register within the selected MMD
1245 * device.
1246 */
1247 int (*read_mmd)(struct phy_device *dev, int devnum, u16 regnum);
1248
1249 /**
1250 * @write_mmd: PHY specific driver override for writing a MMD
1251 * register. This function is optional for PHY specific
1252 * drivers. When not provided, the default MMD write function
1253 * will be used by phy_write_mmd(), which will use either a
1254 * direct write for Clause 45 PHYs, or an indirect write for
1255 * Clause 22 PHYs. devnum is the MMD device number within the
1256 * PHY device, regnum is the register within the selected MMD
1257 * device. val is the value to be written.
1258 */
1259 int (*write_mmd)(struct phy_device *dev, int devnum, u16 regnum,
1260 u16 val);
1261
1262 /** @read_page: Return the current PHY register page number */
1263 int (*read_page)(struct phy_device *dev);
1264 /** @write_page: Set the current PHY register page number */
1265 int (*write_page)(struct phy_device *dev, int page);
1266
1267 /**
1268 * @module_info: Get the size and type of the eeprom contained
1269 * within a plug-in module
1270 */
1271 int (*module_info)(struct phy_device *dev,
1272 struct ethtool_modinfo *modinfo);
1273
1274 /**
1275 * @module_eeprom: Get the eeprom information from the plug-in
1276 * module
1277 */
1278 int (*module_eeprom)(struct phy_device *dev,
1279 struct ethtool_eeprom *ee, u8 *data);
1280
1281 /** @cable_test_start: Start a cable test */
1282 int (*cable_test_start)(struct phy_device *dev);
1283
1284 /** @cable_test_tdr_start: Start a raw TDR cable test */
1285 int (*cable_test_tdr_start)(struct phy_device *dev,
1286 const struct phy_tdr_config *config);
1287
1288 /**
1289 * @cable_test_get_status: Once per second, or on interrupt,
1290 * request the status of the test.
1291 */
1292 int (*cable_test_get_status)(struct phy_device *dev, bool *finished);
1293
1294 /* Get statistics from the PHY using ethtool */
1295 /**
1296 * @get_phy_stats: Retrieve PHY statistics.
1297 * @dev: The PHY device for which the statistics are retrieved.
1298 * @eth_stats: structure where Ethernet PHY stats will be stored.
1299 * @stats: structure where additional PHY-specific stats will be stored.
1300 *
1301 * Retrieves the supported PHY statistics and populates the provided
1302 * structures. The input structures are pre-initialized with
1303 * `ETHTOOL_STAT_NOT_SET`, and the driver must only modify members
1304 * corresponding to supported statistics. Unmodified members will remain
1305 * set to `ETHTOOL_STAT_NOT_SET` and will not be returned to userspace.
1306 */
1307 void (*get_phy_stats)(struct phy_device *dev,
1308 struct ethtool_eth_phy_stats *eth_stats,
1309 struct ethtool_phy_stats *stats);
1310
1311 /**
1312 * @get_link_stats: Retrieve link statistics.
1313 * @dev: The PHY device for which the statistics are retrieved.
1314 * @link_stats: structure where link-specific stats will be stored.
1315 *
1316 * Retrieves link-related statistics for the given PHY device. The input
1317 * structure is pre-initialized with `ETHTOOL_STAT_NOT_SET`, and the
1318 * driver must only modify members corresponding to supported
1319 * statistics. Unmodified members will remain set to
1320 * `ETHTOOL_STAT_NOT_SET` and will not be returned to userspace.
1321 */
1322 void (*get_link_stats)(struct phy_device *dev,
1323 struct ethtool_link_ext_stats *link_stats);
1324
1325 /**
1326 * @update_stats: Trigger periodic statistics updates.
1327 * @dev: The PHY device for which statistics updates are triggered.
1328 *
1329 * Periodically gathers statistics from the PHY device to update locally
1330 * maintained 64-bit counters. This is necessary for PHYs that implement
1331 * reduced-width counters (e.g., 16-bit or 32-bit) which can overflow
1332 * more frequently compared to 64-bit counters. By invoking this
1333 * callback, drivers can fetch the current counter values, handle
1334 * overflow detection, and accumulate the results into local 64-bit
1335 * counters for accurate reporting through the `get_phy_stats` and
1336 * `get_link_stats` interfaces.
1337 *
1338 * Return: 0 on success or a negative error code on failure.
1339 */
1340 int (*update_stats)(struct phy_device *dev);
1341
1342 /** @get_sset_count: Number of statistic counters */
1343 int (*get_sset_count)(struct phy_device *dev);
1344 /** @get_strings: Names of the statistic counters */
1345 void (*get_strings)(struct phy_device *dev, u8 *data);
1346 /** @get_stats: Return the statistic counter values */
1347 void (*get_stats)(struct phy_device *dev,
1348 struct ethtool_stats *stats, u64 *data);
1349
1350 /* Get and Set PHY tunables */
1351 /** @get_tunable: Return the value of a tunable */
1352 int (*get_tunable)(struct phy_device *dev,
1353 struct ethtool_tunable *tuna, void *data);
1354 /** @set_tunable: Set the value of a tunable */
1355 int (*set_tunable)(struct phy_device *dev,
1356 struct ethtool_tunable *tuna,
1357 const void *data);
1358 /**
1359 * @set_loopback: Set the loopback mode of the PHY
1360 * enable selects if the loopback mode is enabled or disabled. If the
1361 * loopback mode is enabled, then the speed of the loopback mode can be
1362 * requested with the speed argument. If the speed argument is zero,
1363 * then any speed can be selected. If the speed argument is > 0, then
1364 * this speed shall be selected for the loopback mode or EOPNOTSUPP
1365 * shall be returned if speed selection is not supported.
1366 */
1367 int (*set_loopback)(struct phy_device *dev, bool enable, int speed);
1368 /** @get_sqi: Get the signal quality indication */
1369 int (*get_sqi)(struct phy_device *dev);
1370 /** @get_sqi_max: Get the maximum signal quality indication */
1371 int (*get_sqi_max)(struct phy_device *dev);
1372
1373 /**
1374 * @get_mse_capability: Get capabilities and scale of MSE measurement
1375 * @dev: PHY device
1376 * @cap: Output (filled on success)
1377 *
1378 * Fill @cap with the PHY's MSE capability for the current
1379 * link mode: scale limits (max_average_mse, max_peak_mse), update
1380 * interval (refresh_rate_ps), sample length (num_symbols) and the
1381 * capability bitmask (supported_caps).
1382 *
1383 * Implementations may defer capability report until hardware has
1384 * converged; in that case they should return -EAGAIN and allow the
1385 * caller to retry later.
1386 *
1387 * Return: 0 on success. On failure, returns a negative errno code, such
1388 * as -EOPNOTSUPP if MSE measurement is not supported by the PHY or in
1389 * the current link mode, or -EAGAIN if the capability information is
1390 * not yet available.
1391 */
1392 int (*get_mse_capability)(struct phy_device *dev,
1393 struct phy_mse_capability *cap);
1394
1395 /**
1396 * @get_mse_snapshot: Retrieve a snapshot of MSE diagnostic values
1397 * @dev: PHY device
1398 * @channel: Channel identifier (PHY_MSE_CHANNEL_*)
1399 * @snapshot: Output (filled on success)
1400 *
1401 * Fill @snapshot with a correlated set of MSE values from the most
1402 * recent measurement window.
1403 *
1404 * Callers must validate @channel against supported_caps returned by
1405 * get_mse_capability(). Drivers must not coerce @channel; if the
1406 * requested selector is not implemented by the device or current link
1407 * mode, the operation must fail.
1408 *
1409 * worst_peak_mse is latched and must be treated as read-to-clear.
1410 *
1411 * Return: 0 on success. On failure, returns a negative errno code, such
1412 * as -EOPNOTSUPP if MSE measurement is not supported by the PHY or in
1413 * the current link mode, or -EAGAIN if measurements are not yet
1414 * available.
1415 */
1416 int (*get_mse_snapshot)(struct phy_device *dev,
1417 enum phy_mse_channel channel,
1418 struct phy_mse_snapshot *snapshot);
1419
1420 /* PLCA RS interface */
1421 /** @get_plca_cfg: Return the current PLCA configuration */
1422 int (*get_plca_cfg)(struct phy_device *dev,
1423 struct phy_plca_cfg *plca_cfg);
1424 /** @set_plca_cfg: Set the PLCA configuration */
1425 int (*set_plca_cfg)(struct phy_device *dev,
1426 const struct phy_plca_cfg *plca_cfg);
1427 /** @get_plca_status: Return the current PLCA status info */
1428 int (*get_plca_status)(struct phy_device *dev,
1429 struct phy_plca_status *plca_st);
1430
1431 /**
1432 * @led_brightness_set: Set a PHY LED brightness. Index
1433 * indicates which of the PHYs led should be set. Value
1434 * follows the standard LED class meaning, e.g. LED_OFF,
1435 * LED_HALF, LED_FULL.
1436 */
1437 int (*led_brightness_set)(struct phy_device *dev,
1438 u8 index, enum led_brightness value);
1439
1440 /**
1441 * @led_blink_set: Set a PHY LED blinking. Index indicates
1442 * which of the PHYs led should be configured to blink. Delays
1443 * are in milliseconds and if both are zero then a sensible
1444 * default should be chosen. The call should adjust the
1445 * timings in that case and if it can't match the values
1446 * specified exactly.
1447 */
1448 int (*led_blink_set)(struct phy_device *dev, u8 index,
1449 unsigned long *delay_on,
1450 unsigned long *delay_off);
1451 /**
1452 * @led_hw_is_supported: Can the HW support the given rules.
1453 * @dev: PHY device which has the LED
1454 * @index: Which LED of the PHY device
1455 * @rules The core is interested in these rules
1456 *
1457 * Return 0 if yes, -EOPNOTSUPP if not, or an error code.
1458 */
1459 int (*led_hw_is_supported)(struct phy_device *dev, u8 index,
1460 unsigned long rules);
1461 /**
1462 * @led_hw_control_set: Set the HW to control the LED
1463 * @dev: PHY device which has the LED
1464 * @index: Which LED of the PHY device
1465 * @rules The rules used to control the LED
1466 *
1467 * Returns 0, or a an error code.
1468 */
1469 int (*led_hw_control_set)(struct phy_device *dev, u8 index,
1470 unsigned long rules);
1471 /**
1472 * @led_hw_control_get: Get how the HW is controlling the LED
1473 * @dev: PHY device which has the LED
1474 * @index: Which LED of the PHY device
1475 * @rules Pointer to the rules used to control the LED
1476 *
1477 * Set *@rules to how the HW is currently blinking. Returns 0
1478 * on success, or a error code if the current blinking cannot
1479 * be represented in rules, or some other error happens.
1480 */
1481 int (*led_hw_control_get)(struct phy_device *dev, u8 index,
1482 unsigned long *rules);
1483
1484 /**
1485 * @led_polarity_set: Set the LED polarity modes
1486 * @dev: PHY device which has the LED
1487 * @index: Which LED of the PHY device
1488 * @modes: bitmap of LED polarity modes
1489 *
1490 * Configure LED with all the required polarity modes in @modes
1491 * to make it correctly turn ON or OFF.
1492 *
1493 * Returns 0, or an error code.
1494 */
1495 int (*led_polarity_set)(struct phy_device *dev, int index,
1496 unsigned long modes);
1497
1498 /**
1499 * @get_next_update_time: Get the time until the next update event
1500 * @dev: PHY device
1501 *
1502 * Callback to determine the time (in jiffies) until the next
1503 * update event for the PHY state machine. Allows PHY drivers to
1504 * dynamically adjust polling intervals based on link state or other
1505 * conditions.
1506 *
1507 * Returns the time in jiffies until the next update event.
1508 */
1509 unsigned int (*get_next_update_time)(struct phy_device *dev);
1510};
1511#define to_phy_driver(d) container_of_const(to_mdio_common_driver(d), \
1512 struct phy_driver, mdiodrv)
1513
1514#define PHY_ID_MATCH_EXTACT_MASK GENMASK(31, 0)
1515#define PHY_ID_MATCH_MODEL_MASK GENMASK(31, 4)
1516#define PHY_ID_MATCH_VENDOR_MASK GENMASK(31, 10)
1517
1518#define PHY_ID_MATCH_EXACT(id) .phy_id = (id), .phy_id_mask = PHY_ID_MATCH_EXTACT_MASK
1519#define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = PHY_ID_MATCH_MODEL_MASK
1520#define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = PHY_ID_MATCH_VENDOR_MASK
1521
1522/**
1523 * phy_id_compare - compare @id1 with @id2 taking account of @mask
1524 * @id1: first PHY ID
1525 * @id2: second PHY ID
1526 * @mask: the PHY ID mask, set bits are significant in matching
1527 *
1528 * Return true if the bits from @id1 and @id2 specified by @mask match.
1529 * This uses an equivalent test to (@id & @mask) == (@phy_id & @mask).
1530 */
1531static inline bool phy_id_compare(u32 id1, u32 id2, u32 mask)
1532{
1533 return !((id1 ^ id2) & mask);
1534}
1535
1536/**
1537 * phy_id_compare_vendor - compare @id with @vendor mask
1538 * @id: PHY ID
1539 * @vendor_mask: PHY Vendor mask
1540 *
1541 * Return: true if the bits from @id match @vendor using the
1542 * generic PHY Vendor mask.
1543 */
1544static inline bool phy_id_compare_vendor(u32 id, u32 vendor_mask)
1545{
1546 return phy_id_compare(id1: id, id2: vendor_mask, PHY_ID_MATCH_VENDOR_MASK);
1547}
1548
1549/**
1550 * phy_id_compare_model - compare @id with @model mask
1551 * @id: PHY ID
1552 * @model_mask: PHY Model mask
1553 *
1554 * Return: true if the bits from @id match @model using the
1555 * generic PHY Model mask.
1556 */
1557static inline bool phy_id_compare_model(u32 id, u32 model_mask)
1558{
1559 return phy_id_compare(id1: id, id2: model_mask, PHY_ID_MATCH_MODEL_MASK);
1560}
1561
1562/**
1563 * phydev_id_compare - compare @id with the PHY's Clause 22 ID
1564 * @phydev: the PHY device
1565 * @id: the PHY ID to be matched
1566 *
1567 * Compare the @phydev clause 22 ID with the provided @id and return true or
1568 * false depending whether it matches, using the bound driver mask. The
1569 * @phydev must be bound to a driver.
1570 */
1571static inline bool phydev_id_compare(struct phy_device *phydev, u32 id)
1572{
1573 return phy_id_compare(id1: id, id2: phydev->phy_id, mask: phydev->drv->phy_id_mask);
1574}
1575
1576const char *phy_speed_to_str(int speed);
1577const char *phy_duplex_to_str(unsigned int duplex);
1578const char *phy_rate_matching_to_str(int rate_matching);
1579
1580int phy_interface_num_ports(phy_interface_t interface);
1581
1582/**
1583 * phy_is_started - Convenience function to check whether PHY is started
1584 * @phydev: The phy_device struct
1585 */
1586static inline bool phy_is_started(struct phy_device *phydev)
1587{
1588 return phydev->state >= PHY_UP;
1589}
1590
1591/**
1592 * phy_driver_is_genphy - Convenience function to check whether PHY is driven
1593 * by one of the generic PHY drivers
1594 * @phydev: The phy_device struct
1595 * Return: true if PHY is driven by one of the genphy drivers
1596 */
1597static inline bool phy_driver_is_genphy(struct phy_device *phydev)
1598{
1599 return phydev->is_genphy_driven;
1600}
1601
1602/**
1603 * phy_disable_eee_mode - Don't advertise an EEE mode.
1604 * @phydev: The phy_device struct
1605 * @link_mode: The EEE mode to be disabled
1606 */
1607static inline void phy_disable_eee_mode(struct phy_device *phydev, u32 link_mode)
1608{
1609 WARN_ON(phy_is_started(phydev));
1610
1611 linkmode_set_bit(link_mode, phydev->eee_disabled_modes);
1612 linkmode_clear_bit(link_mode, phydev->advertising_eee);
1613}
1614
1615/**
1616 * phy_can_wakeup() - indicate whether PHY has driver model wakeup capabilities
1617 * @phydev: The phy_device struct
1618 *
1619 * Returns: true/false depending on the PHY driver's device_set_wakeup_capable()
1620 * setting.
1621 */
1622static inline bool phy_can_wakeup(struct phy_device *phydev)
1623{
1624 return device_can_wakeup(dev: &phydev->mdio.dev);
1625}
1626
1627/**
1628 * phy_may_wakeup() - indicate whether PHY has wakeup enabled
1629 * @phydev: The phy_device struct
1630 *
1631 * Returns: true/false depending on the PHY driver's device_set_wakeup_enabled()
1632 * setting if using the driver model, otherwise the legacy determination.
1633 */
1634bool phy_may_wakeup(struct phy_device *phydev);
1635
1636void phy_resolve_aneg_pause(struct phy_device *phydev);
1637void phy_resolve_aneg_linkmode(struct phy_device *phydev);
1638
1639/**
1640 * phy_read - Convenience function for reading a given PHY register
1641 * @phydev: the phy_device struct
1642 * @regnum: register number to read
1643 *
1644 * NOTE: MUST NOT be called from interrupt context,
1645 * because the bus read/write functions may wait for an interrupt
1646 * to conclude the operation.
1647 */
1648static inline int phy_read(struct phy_device *phydev, u32 regnum)
1649{
1650 return mdiobus_read(bus: phydev->mdio.bus, addr: phydev->mdio.addr, regnum);
1651}
1652
1653#define phy_read_poll_timeout(phydev, regnum, val, cond, sleep_us, \
1654 timeout_us, sleep_before_read) \
1655({ \
1656 int __ret, __val; \
1657 __ret = read_poll_timeout(__val = phy_read, val, \
1658 __val < 0 || (cond), \
1659 sleep_us, timeout_us, sleep_before_read, phydev, regnum); \
1660 if (__val < 0) \
1661 __ret = __val; \
1662 if (__ret) \
1663 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
1664 __ret; \
1665})
1666
1667/**
1668 * __phy_read - convenience function for reading a given PHY register
1669 * @phydev: the phy_device struct
1670 * @regnum: register number to read
1671 *
1672 * The caller must have taken the MDIO bus lock.
1673 */
1674static inline int __phy_read(struct phy_device *phydev, u32 regnum)
1675{
1676 return __mdiobus_read(bus: phydev->mdio.bus, addr: phydev->mdio.addr, regnum);
1677}
1678
1679/**
1680 * phy_write - Convenience function for writing a given PHY register
1681 * @phydev: the phy_device struct
1682 * @regnum: register number to write
1683 * @val: value to write to @regnum
1684 *
1685 * NOTE: MUST NOT be called from interrupt context,
1686 * because the bus read/write functions may wait for an interrupt
1687 * to conclude the operation.
1688 */
1689static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
1690{
1691 return mdiobus_write(bus: phydev->mdio.bus, addr: phydev->mdio.addr, regnum, val);
1692}
1693
1694/**
1695 * __phy_write - Convenience function for writing a given PHY register
1696 * @phydev: the phy_device struct
1697 * @regnum: register number to write
1698 * @val: value to write to @regnum
1699 *
1700 * The caller must have taken the MDIO bus lock.
1701 */
1702static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val)
1703{
1704 return __mdiobus_write(bus: phydev->mdio.bus, addr: phydev->mdio.addr, regnum,
1705 val);
1706}
1707
1708/**
1709 * __phy_modify_changed() - Convenience function for modifying a PHY register
1710 * @phydev: a pointer to a &struct phy_device
1711 * @regnum: register number
1712 * @mask: bit mask of bits to clear
1713 * @set: bit mask of bits to set
1714 *
1715 * Unlocked helper function which allows a PHY register to be modified as
1716 * new register value = (old register value & ~mask) | set
1717 *
1718 * Returns negative errno, 0 if there was no change, and 1 in case of change
1719 */
1720static inline int __phy_modify_changed(struct phy_device *phydev, u32 regnum,
1721 u16 mask, u16 set)
1722{
1723 return __mdiobus_modify_changed(bus: phydev->mdio.bus, addr: phydev->mdio.addr,
1724 regnum, mask, set);
1725}
1726
1727/*
1728 * phy_read_mmd - Convenience function for reading a register
1729 * from an MMD on a given PHY.
1730 */
1731int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
1732
1733/**
1734 * phy_read_mmd_poll_timeout - Periodically poll a PHY register until a
1735 * condition is met or a timeout occurs
1736 *
1737 * @phydev: The phy_device struct
1738 * @devaddr: The MMD to read from
1739 * @regnum: The register on the MMD to read
1740 * @val: Variable to read the register into
1741 * @cond: Break condition (usually involving @val)
1742 * @sleep_us: Maximum time to sleep between reads in us (0 tight-loops). Please
1743 * read usleep_range() function description for details and
1744 * limitations.
1745 * @timeout_us: Timeout in us, 0 means never timeout
1746 * @sleep_before_read: if it is true, sleep @sleep_us before read.
1747 *
1748 * Returns: 0 on success and -ETIMEDOUT upon a timeout. In either
1749 * case, the last read value at @args is stored in @val. Must not
1750 * be called from atomic context if sleep_us or timeout_us are used.
1751 */
1752#define phy_read_mmd_poll_timeout(phydev, devaddr, regnum, val, cond, \
1753 sleep_us, timeout_us, sleep_before_read) \
1754({ \
1755 int __ret, __val; \
1756 __ret = read_poll_timeout(__val = phy_read_mmd, val, \
1757 __val < 0 || (cond), \
1758 sleep_us, timeout_us, sleep_before_read, \
1759 phydev, devaddr, regnum); \
1760 if (__val < 0) \
1761 __ret = __val; \
1762 if (__ret) \
1763 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
1764 __ret; \
1765})
1766
1767/*
1768 * __phy_read_mmd - Convenience function for reading a register
1769 * from an MMD on a given PHY.
1770 */
1771int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
1772
1773/*
1774 * phy_write_mmd - Convenience function for writing a register
1775 * on an MMD on a given PHY.
1776 */
1777int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
1778
1779/*
1780 * __phy_write_mmd - Convenience function for writing a register
1781 * on an MMD on a given PHY.
1782 */
1783int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
1784
1785int __phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask,
1786 u16 set);
1787int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask,
1788 u16 set);
1789int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
1790int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
1791
1792int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
1793 u16 mask, u16 set);
1794int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
1795 u16 mask, u16 set);
1796int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
1797 u16 mask, u16 set);
1798int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
1799 u16 mask, u16 set);
1800
1801/**
1802 * __phy_set_bits - Convenience function for setting bits in a PHY register
1803 * @phydev: the phy_device struct
1804 * @regnum: register number to write
1805 * @val: bits to set
1806 *
1807 * The caller must have taken the MDIO bus lock.
1808 */
1809static inline int __phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val)
1810{
1811 return __phy_modify(phydev, regnum, mask: 0, set: val);
1812}
1813
1814/**
1815 * __phy_clear_bits - Convenience function for clearing bits in a PHY register
1816 * @phydev: the phy_device struct
1817 * @regnum: register number to write
1818 * @val: bits to clear
1819 *
1820 * The caller must have taken the MDIO bus lock.
1821 */
1822static inline int __phy_clear_bits(struct phy_device *phydev, u32 regnum,
1823 u16 val)
1824{
1825 return __phy_modify(phydev, regnum, mask: val, set: 0);
1826}
1827
1828/**
1829 * phy_set_bits - Convenience function for setting bits in a PHY register
1830 * @phydev: the phy_device struct
1831 * @regnum: register number to write
1832 * @val: bits to set
1833 */
1834static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val)
1835{
1836 return phy_modify(phydev, regnum, mask: 0, set: val);
1837}
1838
1839/**
1840 * phy_clear_bits - Convenience function for clearing bits in a PHY register
1841 * @phydev: the phy_device struct
1842 * @regnum: register number to write
1843 * @val: bits to clear
1844 */
1845static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val)
1846{
1847 return phy_modify(phydev, regnum, mask: val, set: 0);
1848}
1849
1850/**
1851 * __phy_set_bits_mmd - Convenience function for setting bits in a register
1852 * on MMD
1853 * @phydev: the phy_device struct
1854 * @devad: the MMD containing register to modify
1855 * @regnum: register number to modify
1856 * @val: bits to set
1857 *
1858 * The caller must have taken the MDIO bus lock.
1859 */
1860static inline int __phy_set_bits_mmd(struct phy_device *phydev, int devad,
1861 u32 regnum, u16 val)
1862{
1863 return __phy_modify_mmd(phydev, devad, regnum, mask: 0, set: val);
1864}
1865
1866/**
1867 * __phy_clear_bits_mmd - Convenience function for clearing bits in a register
1868 * on MMD
1869 * @phydev: the phy_device struct
1870 * @devad: the MMD containing register to modify
1871 * @regnum: register number to modify
1872 * @val: bits to clear
1873 *
1874 * The caller must have taken the MDIO bus lock.
1875 */
1876static inline int __phy_clear_bits_mmd(struct phy_device *phydev, int devad,
1877 u32 regnum, u16 val)
1878{
1879 return __phy_modify_mmd(phydev, devad, regnum, mask: val, set: 0);
1880}
1881
1882/**
1883 * phy_set_bits_mmd - Convenience function for setting bits in a register
1884 * on MMD
1885 * @phydev: the phy_device struct
1886 * @devad: the MMD containing register to modify
1887 * @regnum: register number to modify
1888 * @val: bits to set
1889 */
1890static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
1891 u32 regnum, u16 val)
1892{
1893 return phy_modify_mmd(phydev, devad, regnum, mask: 0, set: val);
1894}
1895
1896/**
1897 * phy_clear_bits_mmd - Convenience function for clearing bits in a register
1898 * on MMD
1899 * @phydev: the phy_device struct
1900 * @devad: the MMD containing register to modify
1901 * @regnum: register number to modify
1902 * @val: bits to clear
1903 */
1904static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
1905 u32 regnum, u16 val)
1906{
1907 return phy_modify_mmd(phydev, devad, regnum, mask: val, set: 0);
1908}
1909
1910/**
1911 * phy_interrupt_is_valid - Convenience function for testing a given PHY irq
1912 * @phydev: the phy_device struct
1913 *
1914 * NOTE: must be kept in sync with addition/removal of PHY_POLL and
1915 * PHY_MAC_INTERRUPT
1916 */
1917static inline bool phy_interrupt_is_valid(struct phy_device *phydev)
1918{
1919 return phydev->irq != PHY_POLL && phydev->irq != PHY_MAC_INTERRUPT;
1920}
1921
1922/**
1923 * phy_polling_mode - Convenience function for testing whether polling is
1924 * used to detect PHY status changes
1925 * @phydev: the phy_device struct
1926 */
1927static inline bool phy_polling_mode(struct phy_device *phydev)
1928{
1929 if (phydev->state == PHY_CABLETEST)
1930 if (phydev->drv->flags & PHY_POLL_CABLE_TEST)
1931 return true;
1932
1933 if (phydev->drv->update_stats)
1934 return true;
1935
1936 return phydev->irq == PHY_POLL;
1937}
1938
1939/**
1940 * phy_has_hwtstamp - Tests whether a PHY time stamp configuration.
1941 * @phydev: the phy_device struct
1942 */
1943static inline bool phy_has_hwtstamp(struct phy_device *phydev)
1944{
1945 return phydev && phydev->mii_ts && phydev->mii_ts->hwtstamp_set;
1946}
1947
1948/**
1949 * phy_has_rxtstamp - Tests whether a PHY supports receive time stamping.
1950 * @phydev: the phy_device struct
1951 */
1952static inline bool phy_has_rxtstamp(struct phy_device *phydev)
1953{
1954 return phydev && phydev->mii_ts && phydev->mii_ts->rxtstamp;
1955}
1956
1957/**
1958 * phy_has_tsinfo - Tests whether a PHY reports time stamping and/or
1959 * PTP hardware clock capabilities.
1960 * @phydev: the phy_device struct
1961 */
1962static inline bool phy_has_tsinfo(struct phy_device *phydev)
1963{
1964 return phydev && phydev->mii_ts && phydev->mii_ts->ts_info;
1965}
1966
1967/**
1968 * phy_has_txtstamp - Tests whether a PHY supports transmit time stamping.
1969 * @phydev: the phy_device struct
1970 */
1971static inline bool phy_has_txtstamp(struct phy_device *phydev)
1972{
1973 return phydev && phydev->mii_ts && phydev->mii_ts->txtstamp;
1974}
1975
1976static inline int phy_hwtstamp(struct phy_device *phydev,
1977 struct kernel_hwtstamp_config *cfg,
1978 struct netlink_ext_ack *extack)
1979{
1980 return phydev->mii_ts->hwtstamp_set(phydev->mii_ts, cfg, extack);
1981}
1982
1983static inline bool phy_rxtstamp(struct phy_device *phydev, struct sk_buff *skb,
1984 int type)
1985{
1986 return phydev->mii_ts->rxtstamp(phydev->mii_ts, skb, type);
1987}
1988
1989static inline int phy_ts_info(struct phy_device *phydev,
1990 struct kernel_ethtool_ts_info *tsinfo)
1991{
1992 return phydev->mii_ts->ts_info(phydev->mii_ts, tsinfo);
1993}
1994
1995static inline void phy_txtstamp(struct phy_device *phydev, struct sk_buff *skb,
1996 int type)
1997{
1998 phydev->mii_ts->txtstamp(phydev->mii_ts, skb, type);
1999}
2000
2001/**
2002 * phy_is_default_hwtstamp - Is the PHY hwtstamp the default timestamp
2003 * @phydev: Pointer to phy_device
2004 *
2005 * This is used to get default timestamping device taking into account
2006 * the new API choice, which is selecting the timestamping from MAC by
2007 * default if the phydev does not have default_timestamp flag enabled.
2008 *
2009 * Return: True if phy is the default hw timestamp, false otherwise.
2010 */
2011static inline bool phy_is_default_hwtstamp(struct phy_device *phydev)
2012{
2013 return phy_has_hwtstamp(phydev) && phydev->default_timestamp;
2014}
2015
2016/**
2017 * phy_on_sfp - Convenience function for testing if a PHY is on an SFP module
2018 * @phydev: the phy_device struct
2019 */
2020static inline bool phy_on_sfp(struct phy_device *phydev)
2021{
2022 return phydev->is_on_sfp_module;
2023}
2024
2025/**
2026 * phy_interface_mode_is_rgmii - Convenience function for testing if a
2027 * PHY interface mode is RGMII (all variants)
2028 * @mode: the &phy_interface_t enum
2029 */
2030static inline bool phy_interface_mode_is_rgmii(phy_interface_t mode)
2031{
2032 return mode >= PHY_INTERFACE_MODE_RGMII &&
2033 mode <= PHY_INTERFACE_MODE_RGMII_TXID;
2034};
2035
2036/**
2037 * phy_interface_mode_is_8023z() - does the PHY interface mode use 802.3z
2038 * negotiation
2039 * @mode: one of &enum phy_interface_t
2040 *
2041 * Returns true if the PHY interface mode uses the 16-bit negotiation
2042 * word as defined in 802.3z. (See 802.3-2015 37.2.1 Config_Reg encoding)
2043 */
2044static inline bool phy_interface_mode_is_8023z(phy_interface_t mode)
2045{
2046 return mode == PHY_INTERFACE_MODE_1000BASEX ||
2047 mode == PHY_INTERFACE_MODE_2500BASEX;
2048}
2049
2050/**
2051 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
2052 * is RGMII (all variants)
2053 * @phydev: the phy_device struct
2054 */
2055static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
2056{
2057 return phy_interface_mode_is_rgmii(mode: phydev->interface);
2058};
2059
2060/**
2061 * phy_is_pseudo_fixed_link - Convenience function for testing if this
2062 * PHY is the CPU port facing side of an Ethernet switch, or similar.
2063 * @phydev: the phy_device struct
2064 */
2065static inline bool phy_is_pseudo_fixed_link(struct phy_device *phydev)
2066{
2067 return phydev->is_pseudo_fixed_link;
2068}
2069
2070phy_interface_t phy_fix_phy_mode_for_mac_delays(phy_interface_t interface,
2071 bool mac_txid, bool mac_rxid);
2072
2073int phy_save_page(struct phy_device *phydev);
2074int phy_select_page(struct phy_device *phydev, int page);
2075int phy_restore_page(struct phy_device *phydev, int oldpage, int ret);
2076int phy_read_paged(struct phy_device *phydev, int page, u32 regnum);
2077int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val);
2078int phy_modify_paged_changed(struct phy_device *phydev, int page, u32 regnum,
2079 u16 mask, u16 set);
2080int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum,
2081 u16 mask, u16 set);
2082
2083struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id,
2084 bool is_c45,
2085 struct phy_c45_device_ids *c45_ids);
2086int fwnode_get_phy_id(struct fwnode_handle *fwnode, u32 *phy_id);
2087struct mdio_device *fwnode_mdio_find_device(struct fwnode_handle *fwnode);
2088struct phy_device *fwnode_phy_find_device(struct fwnode_handle *phy_fwnode);
2089struct fwnode_handle *fwnode_get_phy_node(const struct fwnode_handle *fwnode);
2090struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45);
2091int phy_device_register(struct phy_device *phy);
2092void phy_device_free(struct phy_device *phydev);
2093void phy_device_remove(struct phy_device *phydev);
2094int phy_get_c45_ids(struct phy_device *phydev);
2095int phy_init_hw(struct phy_device *phydev);
2096int phy_suspend(struct phy_device *phydev);
2097int phy_resume(struct phy_device *phydev);
2098int __phy_resume(struct phy_device *phydev);
2099int phy_loopback(struct phy_device *phydev, bool enable, int speed);
2100int phy_sfp_connect_phy(void *upstream, struct phy_device *phy);
2101void phy_sfp_disconnect_phy(void *upstream, struct phy_device *phy);
2102void phy_sfp_attach(void *upstream, struct sfp_bus *bus);
2103void phy_sfp_detach(void *upstream, struct sfp_bus *bus);
2104int phy_sfp_probe(struct phy_device *phydev,
2105 const struct sfp_upstream_ops *ops);
2106struct phy_device *phy_attach(struct net_device *dev, const char *bus_id,
2107 phy_interface_t interface);
2108struct phy_device *phy_find_next(struct mii_bus *bus, struct phy_device *pos);
2109int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
2110 u32 flags, phy_interface_t interface);
2111int phy_connect_direct(struct net_device *dev, struct phy_device *phydev,
2112 void (*handler)(struct net_device *),
2113 phy_interface_t interface);
2114struct phy_device *phy_connect(struct net_device *dev, const char *bus_id,
2115 void (*handler)(struct net_device *),
2116 phy_interface_t interface);
2117void phy_disconnect(struct phy_device *phydev);
2118void phy_detach(struct phy_device *phydev);
2119void phy_start(struct phy_device *phydev);
2120void phy_stop(struct phy_device *phydev);
2121int phy_config_aneg(struct phy_device *phydev);
2122int _phy_start_aneg(struct phy_device *phydev);
2123int phy_start_aneg(struct phy_device *phydev);
2124int phy_aneg_done(struct phy_device *phydev);
2125unsigned int phy_inband_caps(struct phy_device *phydev,
2126 phy_interface_t interface);
2127int phy_config_inband(struct phy_device *phydev, unsigned int modes);
2128int phy_speed_down(struct phy_device *phydev, bool sync);
2129int phy_speed_up(struct phy_device *phydev);
2130bool phy_check_valid(int speed, int duplex, unsigned long *features);
2131
2132int phy_restart_aneg(struct phy_device *phydev);
2133int phy_reset_after_clk_enable(struct phy_device *phydev);
2134
2135static inline struct phy_device *phy_find_first(struct mii_bus *bus)
2136{
2137 return phy_find_next(bus, NULL);
2138}
2139
2140#define mdiobus_for_each_phy(_bus, _phydev) \
2141 for (_phydev = phy_find_first(_bus); _phydev; \
2142 _phydev = phy_find_next(_bus, _phydev))
2143
2144#if IS_ENABLED(CONFIG_PHYLIB)
2145int phy_start_cable_test(struct phy_device *phydev,
2146 struct netlink_ext_ack *extack);
2147int phy_start_cable_test_tdr(struct phy_device *phydev,
2148 struct netlink_ext_ack *extack,
2149 const struct phy_tdr_config *config);
2150#else
2151static inline
2152int phy_start_cable_test(struct phy_device *phydev,
2153 struct netlink_ext_ack *extack)
2154{
2155 NL_SET_ERR_MSG(extack, "Kernel not compiled with PHYLIB support");
2156 return -EOPNOTSUPP;
2157}
2158static inline
2159int phy_start_cable_test_tdr(struct phy_device *phydev,
2160 struct netlink_ext_ack *extack,
2161 const struct phy_tdr_config *config)
2162{
2163 NL_SET_ERR_MSG(extack, "Kernel not compiled with PHYLIB support");
2164 return -EOPNOTSUPP;
2165}
2166#endif
2167
2168static inline void phy_device_reset(struct phy_device *phydev, int value)
2169{
2170 mdio_device_reset(mdiodev: &phydev->mdio, value);
2171}
2172
2173#define phydev_err(_phydev, format, args...) \
2174 dev_err(&_phydev->mdio.dev, format, ##args)
2175
2176#define phydev_err_probe(_phydev, err, format, args...) \
2177 dev_err_probe(&_phydev->mdio.dev, err, format, ##args)
2178
2179#define phydev_info(_phydev, format, args...) \
2180 dev_info(&_phydev->mdio.dev, format, ##args)
2181
2182#define phydev_warn(_phydev, format, args...) \
2183 dev_warn(&_phydev->mdio.dev, format, ##args)
2184
2185#define phydev_dbg(_phydev, format, args...) \
2186 dev_dbg(&_phydev->mdio.dev, format, ##args)
2187
2188static inline const char *phydev_name(const struct phy_device *phydev)
2189{
2190 return dev_name(dev: &phydev->mdio.dev);
2191}
2192
2193static inline void phy_lock_mdio_bus(struct phy_device *phydev)
2194{
2195 mutex_lock(&phydev->mdio.bus->mdio_lock);
2196}
2197
2198static inline void phy_unlock_mdio_bus(struct phy_device *phydev)
2199{
2200 mutex_unlock(lock: &phydev->mdio.bus->mdio_lock);
2201}
2202
2203void phy_attached_print(struct phy_device *phydev, const char *fmt, ...)
2204 __printf(2, 3);
2205char *phy_attached_info_irq(struct phy_device *phydev)
2206 __malloc;
2207void phy_attached_info(struct phy_device *phydev);
2208
2209int genphy_match_phy_device(struct phy_device *phydev,
2210 const struct phy_driver *phydrv);
2211
2212/* Clause 22 PHY */
2213int genphy_read_abilities(struct phy_device *phydev);
2214int genphy_setup_forced(struct phy_device *phydev);
2215int genphy_restart_aneg(struct phy_device *phydev);
2216int genphy_check_and_restart_aneg(struct phy_device *phydev, bool restart);
2217int __genphy_config_aneg(struct phy_device *phydev, bool changed);
2218int genphy_aneg_done(struct phy_device *phydev);
2219int genphy_update_link(struct phy_device *phydev);
2220int genphy_read_lpa(struct phy_device *phydev);
2221int genphy_read_status_fixed(struct phy_device *phydev);
2222int genphy_read_status(struct phy_device *phydev);
2223int genphy_read_master_slave(struct phy_device *phydev);
2224int genphy_suspend(struct phy_device *phydev);
2225int genphy_resume(struct phy_device *phydev);
2226int genphy_loopback(struct phy_device *phydev, bool enable, int speed);
2227int genphy_soft_reset(struct phy_device *phydev);
2228irqreturn_t genphy_handle_interrupt_no_ack(struct phy_device *phydev);
2229
2230static inline int genphy_config_aneg(struct phy_device *phydev)
2231{
2232 return __genphy_config_aneg(phydev, changed: false);
2233}
2234
2235static inline int genphy_no_config_intr(struct phy_device *phydev)
2236{
2237 return 0;
2238}
2239int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad,
2240 u16 regnum);
2241int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum,
2242 u16 regnum, u16 val);
2243
2244/* Clause 37 */
2245int genphy_c37_config_aneg(struct phy_device *phydev);
2246int genphy_c37_read_status(struct phy_device *phydev, bool *changed);
2247
2248/* Clause 45 PHY */
2249int genphy_c45_restart_aneg(struct phy_device *phydev);
2250int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart);
2251int genphy_c45_aneg_done(struct phy_device *phydev);
2252int genphy_c45_read_link(struct phy_device *phydev);
2253int genphy_c45_read_lpa(struct phy_device *phydev);
2254int genphy_c45_read_pma(struct phy_device *phydev);
2255int genphy_c45_pma_setup_forced(struct phy_device *phydev);
2256int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev);
2257int genphy_c45_an_config_aneg(struct phy_device *phydev);
2258int genphy_c45_an_disable_aneg(struct phy_device *phydev);
2259int genphy_c45_read_mdix(struct phy_device *phydev);
2260int genphy_c45_pma_read_abilities(struct phy_device *phydev);
2261int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev);
2262int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev);
2263int genphy_c45_read_eee_abilities(struct phy_device *phydev);
2264int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev);
2265int genphy_c45_read_status(struct phy_device *phydev);
2266int genphy_c45_baset1_read_status(struct phy_device *phydev);
2267int genphy_c45_config_aneg(struct phy_device *phydev);
2268int genphy_c45_loopback(struct phy_device *phydev, bool enable, int speed);
2269int genphy_c45_pma_resume(struct phy_device *phydev);
2270int genphy_c45_pma_suspend(struct phy_device *phydev);
2271int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable);
2272int genphy_c45_plca_get_cfg(struct phy_device *phydev,
2273 struct phy_plca_cfg *plca_cfg);
2274int genphy_c45_plca_set_cfg(struct phy_device *phydev,
2275 const struct phy_plca_cfg *plca_cfg);
2276int genphy_c45_plca_get_status(struct phy_device *phydev,
2277 struct phy_plca_status *plca_st);
2278int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *lp);
2279int genphy_c45_ethtool_get_eee(struct phy_device *phydev,
2280 struct ethtool_keee *data);
2281int genphy_c45_ethtool_set_eee(struct phy_device *phydev,
2282 struct ethtool_keee *data);
2283int genphy_c45_an_config_eee_aneg(struct phy_device *phydev);
2284int genphy_c45_oatc14_cable_test_start(struct phy_device *phydev);
2285int genphy_c45_oatc14_cable_test_get_status(struct phy_device *phydev,
2286 bool *finished);
2287int genphy_c45_oatc14_get_sqi_max(struct phy_device *phydev);
2288int genphy_c45_oatc14_get_sqi(struct phy_device *phydev);
2289
2290/* The gen10g_* functions are the old Clause 45 stub */
2291int gen10g_config_aneg(struct phy_device *phydev);
2292
2293static inline int phy_read_status(struct phy_device *phydev)
2294{
2295 if (!phydev->drv)
2296 return -EIO;
2297
2298 if (phydev->drv->read_status)
2299 return phydev->drv->read_status(phydev);
2300 else
2301 return genphy_read_status(phydev);
2302}
2303
2304void phy_drivers_unregister(struct phy_driver *drv, int n);
2305int phy_drivers_register(struct phy_driver *new_driver, int n,
2306 struct module *owner);
2307void phy_error(struct phy_device *phydev);
2308void phy_state_machine(struct work_struct *work);
2309void phy_trigger_machine(struct phy_device *phydev);
2310void phy_mac_interrupt(struct phy_device *phydev);
2311void phy_start_machine(struct phy_device *phydev);
2312void phy_stop_machine(struct phy_device *phydev);
2313void phy_ethtool_ksettings_get(struct phy_device *phydev,
2314 struct ethtool_link_ksettings *cmd);
2315int phy_ethtool_ksettings_set(struct phy_device *phydev,
2316 const struct ethtool_link_ksettings *cmd);
2317int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd);
2318int phy_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
2319int phy_do_ioctl_running(struct net_device *dev, struct ifreq *ifr, int cmd);
2320int phy_disable_interrupts(struct phy_device *phydev);
2321void phy_request_interrupt(struct phy_device *phydev);
2322void phy_free_interrupt(struct phy_device *phydev);
2323void phy_print_status(struct phy_device *phydev);
2324int phy_get_rate_matching(struct phy_device *phydev,
2325 phy_interface_t iface);
2326void phy_set_max_speed(struct phy_device *phydev, u32 max_speed);
2327void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode);
2328void phy_advertise_supported(struct phy_device *phydev);
2329void phy_advertise_eee_all(struct phy_device *phydev);
2330void phy_support_sym_pause(struct phy_device *phydev);
2331void phy_support_asym_pause(struct phy_device *phydev);
2332void phy_support_eee(struct phy_device *phydev);
2333void phy_disable_eee(struct phy_device *phydev);
2334void phy_set_sym_pause(struct phy_device *phydev, bool rx, bool tx,
2335 bool autoneg);
2336void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx);
2337bool phy_validate_pause(struct phy_device *phydev,
2338 struct ethtool_pauseparam *pp);
2339void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause);
2340
2341s32 phy_get_internal_delay(struct phy_device *phydev, const int *delay_values,
2342 int size, bool is_rx);
2343
2344int phy_get_tx_amplitude_gain(struct phy_device *phydev, struct device *dev,
2345 enum ethtool_link_mode_bit_indices linkmode,
2346 u32 *val);
2347
2348int phy_get_mac_termination(struct phy_device *phydev, struct device *dev,
2349 u32 *val);
2350
2351void phy_resolve_pause(unsigned long *local_adv, unsigned long *partner_adv,
2352 bool *tx_pause, bool *rx_pause);
2353
2354int phy_register_fixup_for_id(const char *bus_id,
2355 int (*run)(struct phy_device *));
2356int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
2357 int (*run)(struct phy_device *));
2358
2359int phy_unregister_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask);
2360int phy_unregister_fixup_for_id(const char *bus_id);
2361int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask);
2362
2363int phy_eee_tx_clock_stop_capable(struct phy_device *phydev);
2364int phy_eee_rx_clock_stop(struct phy_device *phydev, bool clk_stop_enable);
2365int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable);
2366int phy_get_eee_err(struct phy_device *phydev);
2367int phy_ethtool_set_eee(struct phy_device *phydev, struct ethtool_keee *data);
2368int phy_ethtool_get_eee(struct phy_device *phydev, struct ethtool_keee *data);
2369int phy_ethtool_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol);
2370void phy_ethtool_get_wol(struct phy_device *phydev,
2371 struct ethtool_wolinfo *wol);
2372int phy_ethtool_get_link_ksettings(struct net_device *ndev,
2373 struct ethtool_link_ksettings *cmd);
2374int phy_ethtool_set_link_ksettings(struct net_device *ndev,
2375 const struct ethtool_link_ksettings *cmd);
2376int phy_ethtool_nway_reset(struct net_device *ndev);
2377
2378int phy_ethtool_get_strings(struct phy_device *phydev, u8 *data);
2379int phy_ethtool_get_sset_count(struct phy_device *phydev);
2380int phy_ethtool_get_stats(struct phy_device *phydev,
2381 struct ethtool_stats *stats, u64 *data);
2382
2383void __phy_ethtool_get_phy_stats(struct phy_device *phydev,
2384 struct ethtool_eth_phy_stats *phy_stats,
2385 struct ethtool_phy_stats *phydev_stats);
2386void __phy_ethtool_get_link_ext_stats(struct phy_device *phydev,
2387 struct ethtool_link_ext_stats *link_stats);
2388
2389int phy_ethtool_get_plca_cfg(struct phy_device *phydev,
2390 struct phy_plca_cfg *plca_cfg);
2391int phy_ethtool_set_plca_cfg(struct phy_device *phydev,
2392 const struct phy_plca_cfg *plca_cfg,
2393 struct netlink_ext_ack *extack);
2394int phy_ethtool_get_plca_status(struct phy_device *phydev,
2395 struct phy_plca_status *plca_st);
2396
2397int __phy_hwtstamp_get(struct phy_device *phydev,
2398 struct kernel_hwtstamp_config *config);
2399int __phy_hwtstamp_set(struct phy_device *phydev,
2400 struct kernel_hwtstamp_config *config,
2401 struct netlink_ext_ack *extack);
2402
2403extern const struct bus_type mdio_bus_type;
2404extern const struct class mdio_bus_class;
2405
2406/**
2407 * phy_module_driver() - Helper macro for registering PHY drivers
2408 * @__phy_drivers: array of PHY drivers to register
2409 * @__count: Numbers of members in array
2410 *
2411 * Helper macro for PHY drivers which do not do anything special in module
2412 * init/exit. Each module may only use this macro once, and calling it
2413 * replaces module_init() and module_exit().
2414 */
2415#define phy_module_driver(__phy_drivers, __count) \
2416static int __init phy_module_init(void) \
2417{ \
2418 return phy_drivers_register(__phy_drivers, __count, THIS_MODULE); \
2419} \
2420module_init(phy_module_init); \
2421static void __exit phy_module_exit(void) \
2422{ \
2423 phy_drivers_unregister(__phy_drivers, __count); \
2424} \
2425module_exit(phy_module_exit)
2426
2427#define module_phy_driver(__phy_drivers) \
2428 phy_module_driver(__phy_drivers, ARRAY_SIZE(__phy_drivers))
2429
2430#endif /* __PHY_H */
2431

source code of linux/include/linux/phy.h