Papers by Frederic Rothan
A digital delay line compiler is described. Depending on the number of bits per word, the delay r... more A digital delay line compiler is described. Depending on the number of bits per word, the delay required, and the operating frequency, the compiler automatically generates the layout of the block, including output and input buffers and registers for synchronization. The implementation is independent of basic cell characteristics. The architecture is described, as well as the method used for area optimization. Experimental results are discussed
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The HDTV European project EUREKA-95 requires complex video processing to be carried out in the en... more The HDTV European project EUREKA-95 requires complex video processing to be carried out in the encoder. A chip set optimized for large kernel 2D transversal filters, including a programmable delay line and a filter chip, is presented. They can operate at 54 MHz and have been developed in a 1.0 μm CMOS technology. The basic architecture is a modified transposed transversal filter systolic array, where an extra data bus and a 9-b adder are provided in each filter cell to handle the horizontal symmetry. Though expensive compared to a folded data bus, this structure can be pipelined to relax the timing demands for high-speed applications
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This paper discusses a local power supply unit designed for fine grain dynamic voltage scaling (D... more This paper discusses a local power supply unit designed for fine grain dynamic voltage scaling (DVS) in a multi-power domain SoC. The proposed power supply unit is fully compatible with an I/O library and adaptable to various logic module power needs. It delivers the module operating voltage, from 1.2 V to 0.6 V, according to predefined operating power modes and is equipped with the module power gating. The designed circuit requires five-I/O-pad pitch area in a 65-nm technology. The first test chip demonstrates that the maximum power efficiency is over 87% and the measured current consumption in stand-by mode is only 19 nA regardless of the connected module.
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... In an other way, several loads need to be supplied: sensors interface, RF links, digital sign... more ... In an other way, several loads need to be supplied: sensors interface, RF links, digital signal ... A fully autonomous microsystem allowing thermal energy harvesting, power monitoring in the nW range, and power storage in the ... [1] JAParadisoand T.Starner, Energy scavenging for ...
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A wide range of current-sensing techniques has been developed to satisfy various electrical and e... more A wide range of current-sensing techniques has been developed to satisfy various electrical and electronics applications requirements. In high-voltage applications, the main issue is the electrical isolation with accurate measurement at low signal levels. Isolated shunt technology is an attractive and versatile solution for current sensing. Electrical isolated products usually need a power supply at both low and high voltage sides. An original topology that needs only one power supply at the secondary (low voltage) side is reported. In this paper, we introduce an implementation of an integrated shunt current-measurement microsystem based on a 6 kV isolated micro-transformer. This work finds its applications in many domains such as hybrid or electric vehicle battery monitoring or motor control, system building automation or smart grids, where small size and low cost are required.
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This paper proposes an on-chip dc-dc converter for a fine grain IP-level DVS. Linear and switchin... more This paper proposes an on-chip dc-dc converter for a fine grain IP-level DVS. Linear and switching regulators are compared considering this particular application. The chosen buck converter operates with the I/O power supply and uses two discrete devices, a capacitor and an inductor. A test design adaptable to the various operation modes of a logic block is described. Simulation results of the proposed dc-dc converter demonstrate that the maximum power efficiency is over 90% and the leakage current is reduced down to 84 nA.
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Today, a large number of uncooled infrared detector developments are under progress due to the av... more Today, a large number of uncooled infrared detector developments are under progress due to the availability of silicon technology that enables realization of low cost 2D IR arrays. LETI/LIR, which has been involved in this field for a few years, has chosen resistive amorphous silicon as thermometer for its uncooled microbolometer development. After a first phase dedicated to acquisition of the most important detector parameters in order to help the modeling and technological development, an IRCMOS laboratory model (256 X 64 with a pitch of 50 micrometer) was realized and characterized. It was shown that NETD of 70 mK at f/1, 25 Hz and 300 K background can be obtained with high thermal insulation (1.2 107 K/W).
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Today, a large number of uncooled infrared detector developments are under progress due to the av... more Today, a large number of uncooled infrared detector developments are under progress due to the availability of silicon technology that enables realization of low cost 2D IR arrays. LETI/LIR, which has been involved in this field for a few years, has chosen resistive amorphous silicon as thermometer for its uncooled microbolometer development. After a first phase dedicated to acquisition of the most important detector parameters in order to help the modeling and technological development, an IRCMOS laboratory model (256 X 64 with a pitch of 50 micrometer) was realized and characterized. It was shown that NETD of 90 mK at f/1, 25 Hz and 300 K background can be obtained with high thermal insulation (1.2 10(superscript 7) K/W).
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The purpose of this paper is to present the latest developments in Defir (LETI / Sofradir joint l... more The purpose of this paper is to present the latest developments in Defir (LETI / Sofradir joint laboratory) in the field of bi-color and dual band infrared focal plane arrays (FPA) made with HgCdTe. The npn structure is achieved using the Molecular Beam Epitaxy (MBE) technique, planar ion implantation, and both dry and wet etching steps. This back to back diode architecture that allows a perfect spatial coherence with a high field factor and large quantum efficiencies needs only one indium bump connection per pixel. This makes it possible to achieve small pitches (below 25μm) and opens the way to the fabrication of large FPAs (TV/4 to TV) with reasonable wafer sizes. In this paper we present electro optical characterizations of 256x256 prototypes fabricated in Defir operating in two MWIR bands (3.1 and 5μm) with a pitch of 25μm that exhibit background limited performances together with a very high operability (above 99.9%) and NEDT below 22mK for integration time of only 0.5ms. In parallel an industrial product soon available from Sofradir has been developed with a 320x256 format and with a 30μm pitch operating in the same bands. This product exhibits the same operability and NETD as low as 15mK for an integration time as short as 1 ms. Finally, last results regarding 256x256 prototypes operating in MWIR/LWIR bands are presented, together with preliminary APD operating mode for the MWIR photodiodes of this last dual band detector.
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New gallium-doped silicon 128 by 192 element arrays have been achieved at CEA-LETI-LIR (Infrared ... more New gallium-doped silicon 128 by 192 element arrays have been achieved at CEA-LETI-LIR (Infrared Laboratory) for imaging in the 8 - 14 micrometer spectral range. This program is in keeping with the previous detector development for the ISOCAM camera (32 by 32 element arrays) and for ground-based observation (64 by 64 element arrays). The main features of the new detectors are: a pitch of 75 micrometer which leads to 10 by 15 mm2 chip dimensions, two selectable storage capacitors (respectively 0.1 and 0.5 pF), a DVR readout circuit achieved in an NMOS silicon line with 1.5 micrometer design rules. The main electro- optical performances are the following: a peak responsivity of 4.0 A/W, a noise of 58 fA rms over the 0.1 - 128 Hz spectral range which is very close to the BLIP noise, and a corresponding noise equivalent power of 1.4 10-14 W.
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In this paper we present a status of the activity of the LETI infrared laboratory in the field of... more In this paper we present a status of the activity of the LETI infrared laboratory in the field of HgCdTe infrared multispectral detectors. The multilayer doped structures needed to achieve two color pixels are grown by molecular beam epitaxy (MBE) (211)HgCdTe on lattice matched CdZnTe substrates. The device structure is n+ppn and is spatially coherent. The long wavelength layer is a planar like n+/p diode and is made by ion implantation while the shorter wavelength p-n diode is made in-situ during the MBE growth using Indium impurity doping. The last junction is isolated by mesa etch. The detectors are interconnected by indium bumps to a CMOS readout circuit. One or two indium bumps per pixel are used to address sequentially or simultaneously the two wavelengths, the detector pitch being 50micrometers or 60micrometers respectively. Elementary detectors exhibit performances in each band which are very close to those obtained in single color detectors with our standard technology. The Si-CMOS read-out circuits are specially designed to optimize the best performance of the IRCMOS focal plane arrays (FPA) in both wavelengths. The electro-optical performances of a two color IRCMOS FPA with a complexity of 128x128 pixels (pitch of 50micrometers ) operating sequentially within the (3-5micrometers ) middle wavelength infrared range (MWIR) at 77K will be presented.
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New gallium-doped silicon 128 X 192 element arrays have been achieved at CEA-LETI- LIR (Infrared ... more New gallium-doped silicon 128 X 192 element arrays have been achieved at CEA-LETI- LIR (Infrared Laboratory) for imaging in the 8 - 14 micrometers spectral range. This program is in keeping with the previous detector developments for the ISOCAM camera (32 X 32 element arrays) and for ground-based observations (64 X 64 element arrays). The main features of the new detectors are: a pitch of 75 micrometers which leads to 10 X 15 mm(superscript 2) chip dimensions, two selectable storage capacities (respectively 0.1 and 0.5 pF), a DVR readout circuit achieved in an NMOS silicon line with 1.5 micrometers design rules. The main electro-optical performances are the following: a peak responsivity of 4.0 A/W, a noise of 58 fArms over the 0.1 - 128 Hz spectral band which is very close to the BLIP noise, and a corresponding noise equivalent power of 1.4 10(superscript -14) W.
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Journal of Electronic Materials, 2007
In this paper we show the latest achievements of HgCdTe-based infrared bispectral focal plane arr... more In this paper we show the latest achievements of HgCdTe-based infrared bispectral focal plane arrays (FPAs) at LETI infrared laboratory. We present and compare the two different pixel architectures that are studied now in our laboratory, named “NPN” and “pseudo-planar”. With these two technologies, a wide range of system applications in dual-band detection can be covered. Advantages of both architectures will be pointed out. We also review performances obtained with these different architectures. The first one has been studied for several years in our laboratory, and we review results obtained on FPAs of size 256 × 256 pixels on a 25 μm pitch, in the MWIR/MWIR (3 μm/5 μm) range. Very high noise equivalent temperature difference (NETD) operability is obtained, at 99.8% for the λc = 3 μm band and 98.7% for the λc = 5 μm band. The second one has been developed more recently, to address other applications that need temporal coherence as well as spatial coherence. We show detailed performances measured on pseudo-planar type FPAs of size 256 × 256 pixels on a 30 μm pitch, in the MWIR/LWIR (5 μm/9 μm) range. The results are also very promising for these prototypes, with NETD as low as 15 mK for an integration time as short as 1 ms, and good operability. The main manufacturing issues are also presented and discussed for both pixel architectures. Challenging process steps are, firstly, molecular beam epitaxy (MBE) HgCdTe heterostructure growth, on large substrates (cadmium zinc telluride) and heterosubstrates (germanium), and, secondly, detector array fabrication on a nonplanar surface. In particular, trenches or hole etching steps, photolithography and hybridization are crucial to improve uniformity, number of defects and performances. Some results of surface, structural and electrical characterizations are shown to illustrate these issues. On the basis of these results, the short-term and long-term objectives and trends for our research and development are presented, in terms of pixel pitch reduction, wavelengths, and dual-band FPA size.
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CEA/LETI has been working for several years on the development of HgCdTe-based infrared dual band... more CEA/LETI has been working for several years on the development of HgCdTe-based infrared dual band detectors [3]. Since 2001 CEA/LETI is also involved in a large program for the demonstration of dual band QWIP FPAs presenting large format and small pitch. This study is carried out with the QWIP team of THALES Research and Technology (TRT) in charge of QWIP design, MBE growth and GaAs processing for the detector side. As part of this program TRT investigated different quantum structures and pixel architectures for the realization of two-band FPAs for MWIR/LWIR and LWIR/LWIR applications. At the end of this study a choice of the most appropriate architecture was done. On its side, CEA/LETI designed readout circuits optimized for the selected dual-band QWIP. TRT delivered QWIP arrays and CEA/LETI proceeded to the assembly, integration and electro-optical characterization. The aim of this paper is to describe the architecture of these dual-band demonstrators and to present the first results concerning their electro-optical performances measured at 70K and 65K.
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Journal of Electronic Materials, 2006
The purpose of this paper is to present the electro-optical performances of dual-band infrared de... more The purpose of this paper is to present the electro-optical performances of dual-band infrared detectors operating in a fully spatially coherent mode, with a small pixel pitch. The successive steps of device fabrication are first exposed, including molecular beam epitaxy (MBE), technological processing, and readout circuit design. It is shown that very high-quality multiple layer heterostructures of HgCdTe can be grown and processed into 256×256 arrays of 25-µm pitch mesas, each mesa including two photodiodes with different cutoff wavelengths ranging in the midwave infrared (MWIR). Characterization of these focal plane arrays (FPAs) shows very good homogeneity, low defect density, and operabilities usually above 99% for both response and noise equivalent thermal difference (NETD).
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In this paper we present a status of the activity of the LETI infrared laboratory in the field of... more In this paper we present a status of the activity of the LETI infrared laboratory in the field of HgCdTe infrared multispectral detectors. The multilayer doped structures needed to achieve two color pixels are grown by molecular beam epitaxy (MBE) (211)HgCdTe on lattice matched CdZnTe substrates. The device structure is n+ppn and is spatially coherent. The long wavelength layer is a planar like n+/p diode and is made by ion implantation while the shorter wavelength p-n diode is made in-situ during the MBE growth using Indium impurity doping. The last junction is isolated by mesa etch. The detectors are interconnected by indium bumps to a CMOS readout circuit. One or two indium bumps per pixel are used to address sequentially or simultaneously the two wavelengths, the detector pitch being 50micrometers or 60micrometers respectively. Elementary detectors exhibit performances in each band which are very close to those obtained in single color detectors with our standard technology. The Si-CMOS read-out circuits are specially designed to optimize the best performance of the IRCMOS focal plane arrays (FPA) in both wavelengths. The electro-optical performances of a two color IRCMOS FPA with a complexity of 128x128 pixels (pitch of 50micrometers ) operating sequentially within the (3-5micrometers ) middle wavelength infrared range (MWIR) at 77K will be presented.
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Designing a digital IR focal plane array (IRFPA) requires fulfilling very stringent requirements ... more Designing a digital IR focal plane array (IRFPA) requires fulfilling very stringent requirements in terms of power consumption, silicon area and speed. Among the various ADC architectures like successive approximation, ramp or over-sampled converters, the best choice strongly depends on the application. We believe that sigma-delta converters, in spite of their quite high power consumption, are a promising solution for high-performance and medium size FPA, e.g. 320x240. This paper presents the design of a second-order incremental sigma-delta ADC dedicated to cooled (77K) IRFPA applications. System-level simulations used to define the modulator parameters and specify its analog building blocks are presented. Circuit design of the switched-capacitor modulator and the digital decimation filter is described. The column ADC including the filter has been implemented in a standard 0.35μm CMOS process on the basis of a 25μm pitch and lead to a total length of 3200μm. Test chips including a single ADC have been manufactured end of 2006. The first measurement results, at 77K, are presented along with perspectives and future developments. They demonstrate the following performance: 81dB Signal-to-Noise Ratio (SNR), 13 bits Effective Number Of Bits (ENOB) and 270μW power consumption at 17kSamples/s rate.
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Journal of Electronic Materials, 2003
In this article, we present recent developments of the research in France at LETI infrared labora... more In this article, we present recent developments of the research in France at LETI infrared laboratory in the field of complex third-generation HgCdTe IRCMOS focal plane arrays (FPAs). We illustrate this with three prototypes of FPAs made at LETI, which have involved some technological improvements from the standard process today in production at Sofradir. We present, using molecular-beam epitaxy (MBE) growth, a 128 × 128 dual-band infrared (photodetector)-complementary metal oxide semiconductor (IRCMOS) with a pitch of 50 µm operating within 2–5 µm. Using the more conventional liquid-phase epitaxy (LPE) growth, we show a new generation of high-performance long linear arrays (1500 × 2; pitch, 30 µm) operating in medium-wavelength infrared (MWIR) or long-wavelength infrared (LWIR) bands based on a modular architecture of butted HgCdTe detection circuit and SiCMOS multiplexers. Finally, we present for the first time a megapixel (1000 × 1000) FPA with a pitch of 15 µm operating in the MWIR band that exhibits a very high performance and pixel operability.
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Papers by Frederic Rothan